ICS1562B Datasheet, PDF (1/20 Pages) Integrated Circuit Systems – User Programmable Differential Output Graphics Clock Generator

Integrated
Circuit
Systems, Inc.
ICS1562B
User Programmable Differential Output Graphics Clock Generator
Description
Features
The ICS1562B is a very high performance monolithic phase- • Two programming options:
locked loop (PLL) frequency synthesizer. Utilizing ICS’s ad-
ICS1562B-001 (Parallel Programming)
vanced CMOS mixed-mode technology, the ICS1562B
ICS1562B-201 (Serial Programming)
provides a low cost solution for high-end video clock genera-
tion.
•
Supports high-resolution graphics - CLK output to
260 MHz, with 400 MHz options available
The ICS1562B has differential video clock outputs (CLK+ and ^{• Eliminates need for multiple ECL output crystal oscillators}
CLK-) that are compatible with industry standard video DAC. • Fully programmable synthesizer capability - not just a
Another clock output, LOAD, is provided whose frequency is
clock multiplier
derived from the main clock by a programmable divider. An _{• Circuitry included for reset of Brooktree RAMDAC pipe-}
additional clock output is available, LD/N2, which is derived
from the LOAD frequency and whose modulus may also be
line delay
programmed.
• VRAM shift clock generation capability
(-201 option only)
Operating frequencies are fully programmable with direct con- • External feedback loop capability (-201 option only)
trol provided for reference divider, prescaler, feedback divider _{• Compact - 16-pin 0.150” skinny SOIC package}
and post-scaler.
• Fully backward compatible to ICS1562
Reset of the pipeline delay on Brooktree RAMDAC s may
be performed under register control. Outputs may also be set
to desired states to facilitate circuit board testing.
Simplified Block Diagram - ICS1562B
XTAL1
XTAL2
CRYSTAL
OSCILLATOR
/R
PHASE-
FREQUENCY
DETECTOR
 EXTFBK
 _BLANK

(-201 only)
MUX
LOOP
FILTER
CHARGE
PUMP
VCO
PRESCALER
/M
/A
ICS1562B - 001 Pinout
AD0
1
XTAL1
2
XTAL2
3
STROBE
4
VSS
5
VSS
6
LOAD
7
LD/N2
8
16
AD1
15
AD2
14
AD3
13
VDD
12
VDDO
11
IPRG
10
CLK+
9
CLK-
PROGRAMMING
INTERFACE
FEEDBACK DIVIDER
16-Pin SOIC
MUX
/2
/4
DIFF.
OUTPUT
CLK+
CLK−
ICS1562B - 201 Pinout
Figure 1
RAMDAC is a trademark of Brooktree Corporation.
1562 B Rev B 10/07/04
/ N1
MUX
/ N2
DRIVER
DRIVER
LOAD
LD/N2
EXTFBK
XTAL1
XTAL2
DATCLK
VSS
VSS
LOAD
LD/N2
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
16-Pin SOIC
DATA
HOLD
BLANK
VDD
VDDO
IPRG
CLK+
CLK-