ICS1562B Datasheet, PDF (13/20 Pages) Integrated Circuit Systems – User Programmable Differential Output Graphics Clock Generator

BIT(S)
33-38
39
40
41-44
45
46
47
48
49-55
56
BIT REF.
M[0]..M[5]
FBKPOL
DBLFREQ
A[0]..A[3]
RESERVED
LOADEN~
SKEW-
SKEW+
R[0]..R[6]
REFPOL
ICS1562B
DESCRIPTION
M counter control bits
Modulus = value +1
External feedback polarity control bit. The PLL will lock to the falling
edge of EXTFBK when FBKPOL=1 and to the rising edge of EXTFBK
when FBKPOL=0.
Doubles modulus of dual-modulus prescaler (from 6/7 to 12/14).
Controls A counter. When set to zero, modulus=7. Otherwise,
modulus=7 for “value” underflows of the prescaler, and modulus=6
thereafter until M counter underflows.
Set to zero.
Load clock divider enable (active low). When set to logic 1, the LOAD
and LD/N2 outputs will cease toggling.
Differential output duty factor adjust.
SKEW+
0
0
1
1
SKEW-
0
1
0
1
Default
Reduces THIGH by approximately
100 ps
Increases THIGH by approximately
100 ps
Do not use
Reference divider modulus control bits
Modulus = value + 1
PLL locks to the rising edge of XTAL1 input when REFPOL=1 and to
the falling edge of XTAL1 when REFPOL=0.
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