IC61LV6432 Datasheet, PDF (17/21 Pages) Integrated Circuit Systems – 64K x 32 Pipelined Sync. SRAM

IC61LV6432
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)
Symbol Parameter
-166
-133
-117
Min. Max Min. Max. Min. Max. Unit
tKC
Cycle Time
6 — 7.5 — 8.5 —
ns
tKH
Clock High Time
2.4 — 2.8 — 3 —
ns
tKL
Clock Low Time
2.4 — 2.8 — 3 —
ns
tKQ
Clock Access Time
—5
—5—5
ns
tKQX⁽³⁾
Clock High to Output Invalid
1.5 — 1.5 — 1.5 —
ns
tKQLZ^(3,4)
Clock High to Output Low-Z
0—
0—0—
ns
tKQHZ^(3,4)
Clock High to Output High-Z
1.5 5 1.5 5 1.5 6
ns
tOEQ
Output Enable to Output Valid
—5
—5—5
ns
tOEQX⁽³⁾
Output Disable to Output Invalid
0—
0—0—
ns
tOELZ^(3,4)
Output Enable to Output Low-Z
0—
0—0—
ns
tOEHZ^(3,4)
Output Disable to Output High-Z
—3
—3—4
ns
tAS
Address Setup Time
2.5 — 2.5 — 2.5 —
ns
tSS
Address Status Setup Time
2.5 — 2.5 — 2.5 —
ns
tCES
Chip Enable Setup Time
2.5 — 2.5 — 2.5 —
ns
tAH
Address Hold Time
2.5 — 2.5 — 2.5 —
ns
tSH
Address Status Hold Time
2.5 — 2.5 — 2.5 —
ns
tCEH
Chip Enable Hold Time
2.5 — 2.5 — 2.5 —
ns
tZZS⁽⁵⁾
ZZ Standby
2—
2—2—
cyc
tZZREC⁽⁶⁾
ZZ Recovery
2—
2—2—
cyc
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. ADVANCEINFORMATIONONLY.
3. Guaranteed but not 100% tested. This parameter is periodically sampled.
4. Tested with load in Figure 2.
5. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data
retention is guaranteed when ZZ is asserted and clock remains active.
6. ADSC and ADSP must not be asserted for at least two cycles after leaving ZZ state.
Integrated Circuit Solution Inc.
17
SSR005-0A 02/02/2004