IC61LV6432 Datasheet, PDF (11/21 Pages) Integrated Circuit Systems – 64K x 32 Pipelined Sync. SRAM

IC61LV6432
READ CYCLE TIMING: PIPELINE
CLK
ADSP
ADSC
ADV
A15-A0
GW
BWE
tKC
tKH
tKL
tSS
tSH
tSS
tSH
tAVS
tAS
tAH
RD1
tWS
RD2
tWH
tWS
tWH
ADSP is blocked by CE1 inactive
ADSC initiate read
tAVH
Suspend Burst
RD3
BW4-BW1
CE1
CE2
CE3
OE
DATAOUT
DATAIN
tCES
tCEH
CE1 Masks ADSP
tCES
tCEH
tCES
tCEH
tOEQ
CE2 and CE3 only sampled with ADSP or ADSC
tOEHZ
High-Z
High-Z
tOELZ
tKQLZ
tKQ
tOEQX
1a
Single Read
2a
2b
2c
2d
Burst Read
Pipelined Read
Unselected with CE2
tKQX
3a
tKQHZ
Unselected
Integrated Circuit Solution Inc.
11
SSR005-0A 02/02/2004