IC61LV6432 Datasheet, PDF (15/21 Pages) Integrated Circuit Systems – 64K x 32 Pipelined Sync. SRAM

IC61LV6432
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) (Continued)
Symbol
Parameter
-5
-6
-7
-8
Min. Max. Min. Max. Min. Max. Min. Max. Unit
tKC
Cycle Time
10 — 12 — 13 — 15 —
ns
tKH
Clock High Time
3.5 —
4—
6—6—
ns
tKL
Clock Low Time
3.5 —
4—
6—6—
ns
tKQ
Clock Access Time
—5
—6
—7—8
ns
tKQX⁽¹⁾
Clock High to Output Invalid
1.5 — 1.5 —
2—2—
ns
tKQLZ^(1,2)
Clock High to Output Low-Z
0—
0—
0—0—
ns
tKQHZ^(1,2)
Clock High to Output High-Z
1.5 6 1.5 6
2626
ns
tOEQ
Output Enable to Output Valid
—5
—6
—6—6
ns
tOEQX⁽¹⁾
Output Disable to Output Invalid
0—
0—
0—0—
ns
tOELZ^(1,2)
Output Enable to Output Low-Z
0—
0—
0—0—
ns
tOEHZ^(1,2)
Output Disable to Output High-Z
—4
—5
—6—6
ns
tAS
Address Setup Time
2.5 — 2.5 — 2.5 — 2.5 —
ns
tSS
Address Status Setup Time
2.5 — 2.5 — 2.5 — 2.5 —
ns
tWS
Write Setup Time
2.5 — 2.5 — 2.5 — 2.5 —
ns
tCES
Chip Enable Setup Time
2.5 — 2.5 — 2.5 — 2.5 —
ns
tAH
Address Hold Time
0.5 — 0.5 — 0.5 — 0.5 —
ns
tSH
Address Status Hold Time
0.5 — 0.5 — 0.5 — 0.5 —
ns
tWH
Write Hold Time
0.5 — 0.5 — 0.5 — 0.5 —
ns
tCEH
Chip Enable Hold Time
0.5 — 0.5 — 0.5 — 0.5 —
ns
tCFG⁽³⁾
Configuration Setup
35 — 45 — 52 — 60 —
ns
Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
3. Configuration signal MODE is static and must not change during normal operation.
Integrated Circuit Solution Inc.
15
SSR005-0A 02/02/2004