IC61LV6432 Datasheet, PDF (14/21 Pages) Integrated Circuit Systems – 64K x 32 Pipelined Sync. SRAM

IC61LV6432
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol Parameter
-166
Min. Max.
tKC
Cycle Time
6—
tKH
Clock High Time
2.4 —
tKL
Clock Low Time
2.4 —
tKQ
Clock Access Time
—5
tKQX⁽²⁾
Clock High to Output Invalid
1.5 —
tKQLZ^(2,3)
Clock High to Output Low-Z
0—
tKQHZ^(2,3)
Clock High to Output High-Z
1.5 5
tOEQ
Output Enable to Output Valid
—5
tOEQX⁽²⁾
Output Disable to Output Invalid
0—
tOELZ^(2,3)
Output Enable to Output Low-Z
0—
tOEHZ^(2,3)
Output Disable to Output High-Z
—3
tAS
Address Setup Time
2.5 —
tSS
Address Status Setup Time
2.5 —
tWS
Write Setup Time
2.5 —
tCES
Chip Enable Setup Time
2.5 —
tAH
Address Hold Time
0.5 —
tSH
Address Status Hold Time
0.5 —
tWH
Write Hold Time
0.5 —
tCEH
Chip Enable Hold Time
0.5 —
tCFG⁽⁴⁾
Configuration Setup
25 —
Notes:
1. ADVANCE INFORMATION ONLY.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
4. Configuration signal MODE is static and must not change during normal operation.
-133
-117
Min. Max. Min. Max.
7.5 — 8.5 —
2.8 — 3 —
2.8 — 3 —
—5—5
1.5 — 1.5 —
0—0—
1.5 5 1.5 6
—5—5
0—0—
0—0—
—3—4
2.5 — 2.5 —
2.5 — 2.5 —
2.5 — 2.5 —
2.5 — 2.5 —
0.5 — 0.5 —
0.5 — 0.5 —
0.5 — 0.5 —
0.5 — 0.5 —
30 — 35 —
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
14
Integrated Circuit Solution Inc.
SSR005-0A 002/02/2004