IC61LV6432 Datasheet, PDF (12/21 Pages) Integrated Circuit Systems – 64K x 32 Pipelined Sync. SRAM

IC61LV6432
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol
tKC
tKH
tKL
tAS
tSS
tWS
tDS
tCES
tAVS
tAH
tSH
tDH
tWH
tCEH
tAVH
tCFG⁽²⁾
Parameter
Cycle Time
Clock High Time
Clock Low Time
Address Setup Time
Address Status Setup Time
Write Setup Time
Data In Setup Time
Chip Enable Setup Time
Address Advance Setup Time
Address Hold Time
Address Status Hold Time
Data In Hold Time
Write Hold Time
Chip Enable Hold Time
Address Advance Hold Time
Configuration Setup
-166
-133
-117
Min. Max. Min. Max. Min. Max. Unit
6 — 7.5 — 8.5 —
ns
2.4 — 2.8 — 3 —
ns
2.4 — 2.8 — 3 —
ns
2.5 — 2.5 — 2.5 —
ns
2.5 — 2.5 — 2.5 —
ns
2.5 — 2.5 — 2.5 —
ns
2.5 — 2.5 — 2.5 —
ns
2.5 — 2.5 — 2.5 —
ns
2.5 — 2.5 — 2.5 —
ns
0.5 — 0.5 — 0.5 —
ns
0.5 — 0.5 — 0.5 —
ns
0.5 — 0.5 — 0.5 —
ns
0.5 — 0.5 — 0.5 —
ns
0.5 — 0.5 — 0.5 —
ns
0.5 — 0.5 — 0.5 —
ns
25 — 30 — 35 —
ns
Symbol
Parameter
-5
-6
-7
-8
Min. Max. Min. Max. Min. Max. Min. Max. Unit
tKC
Cycle Time
10 — 12 — 13 — 15 —
ns
tKH
Clock High Time
3.5 —
4—
6—6—
ns
tKL
Clock Low Time
3.5 —
4—
6—6—
ns
tAS
Address Setup Time
2.5 — 2.5 — 2.5 — 2.5 —
ns
tSS
Address Status Setup Time
2.5 — 2.5 — 2.5 — 2.5 —
ns
tWS
Write Setup Time
2.5 — 2.5 — 2.5 — 2.5 —
ns
tDS
Data In Setup Time
2.5 — 2.5 — 2.5 — 2.5 —
ns
tCES
Chip Enable Setup Time
2.5 — 2.5 — 2.5 — 2.5 —
ns
tAVS
Address Advance Setup Time
2.5 — 2.5 — 2.5 — 2.5 —
ns
tAH
Address Hold Time
0.5 — 0.5 — 0.5 — 0.5 —
ns
tSH
Address Status Hold Time
0.5 — 0.5 — 0.5 — 0.5 —
ns
tDH
Data In Hold Time
0.5 — 0.5 — 0.5 — 0.5 —
ns
tWH
Write Hold Time
0.5 — 0.5 — 0.5 — 0.5 —
ns
tCEH
Chip Enable Hold Time
0.5 — 0.5 — 0.5 — 0.5 —
ns
tAVH
Address Advance Hold Time
0.5 — 0.5 — 0.5 — 0.5 —
ns
tCFG⁽²⁾
Configuration Setup
35 — 45 — 52 — 60 —
ns
Note:
1. ADVANCE INFORMATION ONLY.
2. Configuration signal MODE is static and must not change during normal operation.
12
Integrated Circuit Solution Inc.
SSR005-0A 002/02/2004