IS61NW6432 Datasheet, PDF (4/14 Pages) Integrated Circuit Solution Inc – 64K x 32 SYNCHRONOUS STATIC RAM WITH NO-WAIT STATE BUS FEATURE

IS61NW6432
TRUTH TABLE⁽¹⁾
Operation
Bein New Write Cycle
Begin New Read Cycle
Advance Burst Counter
(Burst Write)
Advance Burst Counter
(BurstRead)
Deselect (2 Cycle)
Hold/NOOP^"
Address
Used
External
External
Internal
Internal
X
X
R/W
L
H
X
X
X
X
CEx
ADV/LD
L
L
L
L
X
H
X
H
H
L
X
X
CEN
L
L
L
L
L
H
BWx
Valid
X
Valid
X
X
X
CLK
L-H
L-H
L-H
L-H
L-H
L-H
Notes:
1. "X" Means don't care.
2. When ADV/LD signal is sampled HI|GH, the internal burst counter is incremented. The R/W signal is ignored when the counter
is advanced, Therefore, the nature of the burst cycle (Read or Write) is deternined by the status of the R/W signal when the
first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when CEx is sampled HIGH and ADV/LD sampled LOW at rising edge of clock. The data bus will
tristate two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked form propogating through the part. The state
of all the internal registers remains unchanged.
PARTIAL TRUTH TABLE(Non-burst)
Function
GW BW1 BW2 BW3 BW4 CEx ADV/LD
READ
H
X
XX
X
L
L
WRITE Byte 1
L
L
HH
H
L
L
WRITE Byte 2
L
H
LH
H
L
L
WRITE Byte 3
L
H
HL
H
L
L
WRITE Byte 4
L
H
HH
L
L
L
WRITE All Bytes L
L
LL
L
X
L
FUNCTIONAL TIMING DIAGRAM
4
Integrated Circuit Solution Inc.
SSR006-0B