IS61NW6432 Datasheet, PDF (1/14 Pages) Integrated Circuit Solution Inc – 64K x 32 SYNCHRONOUS STATIC RAM WITH NO-WAIT STATE BUS FEATURE

I_IS_S61₆N₁W_N64_W32 ₆₄₃₂
64K x 32 SYNCHRONOUS STATIC RAM
WITH NO-WAIT STATE BUS FEATURE
FEATURES
• Fast access time:
— 5 ns-100 MHz; 6 ns-83 MHz;
— 7 ns-75 MHz; 8ns-66 MHz;
• No wait cycles between Read and write
• Internal self-timed write cycle
• Individual byte write Control
• Clock controlled, registered address, data and
control
• Pentium^TM or Inear burst sequence control using
MODE input
• Three chip enables for simple depth depth
expansion and adress pipelining
• Common data inputs and data outputs
• JEDEC 100-pin LQFP and PQFP package
• Single+3.3V power supply
• Optional data strobe pin (#80) for latching data
(See page 12 for detailed timing)
DESCRIPTION
The IS61NW6432 is a high-speed, low-power synchronous
static RAM designed to provide a burstable, high-performance,
no-wait bus, secondary cache for the Pentium, 680X0, and
Power PC microprocessors. It is organized as 65,536 words
by 32 bits, fabricated with ICSI's advanced CMOS technology.
Incorporating a no-wait bus, wait cycles are eliminated when
the bus switches from read to write, or write to read. This
device integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single monolithic
circuit.
All synchronous inputs pass through registers controlled by a
Positive-edge-trggered clock input. Operations may be sus-
pended and all synchronous inputs ignored when Clock Enable,
CEN is HIGH. In this state the internal device will hold their
previous values.
When the ADV/LD is HIGH the internal burst counter is
incremented. New external addresses can be loaded when
ADV/LD is LOW.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock inputs and when RD/WE is LOW.
Separate byte enables allow indiviual bytes to be written. BW1
controls I/O1-I/P8; BW2 controls I/O9-I/O16;BW3 controls I/
O17-I/O24; BW4 controls I/O25-I/O32. All Bytes are written
when BW1, BW2, BW3, and BW4 are LOW.
MODE pin upon power up is in interleave burst mode. It can be
connected to GND or VccQ to alter power up state.
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
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