IS61NW6432 Datasheet, PDF (11/14 Pages) Integrated Circuit Solution Inc – 64K x 32 SYNCHRONOUS STATIC RAM WITH NO-WAIT STATE BUS FEATURE

IS61NW6432
READ /WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol Parameter
-5
-6
-7
-8
Min. Max. Min. Max. Min. Max Min. Max.
Unit
fmax Clock Frequency
— 100 — 83 — 75 —
66
MHz
tKC
Cycle Time
10
—
12 — 13 — 15
—
ns
tKH
Clock High Time
4
—
4—6—6
—
ns
tKL
Clock Low Time
4
—
4—6—6
—
ns
tKQ
Clock Access Time
—
5
—6—7—
8
ns
tKQX Clock High to Output Invalid
1.5
—
1.5 — 1.5 — 1.5
—
ns
tKQLZ Clock High to Output Low-Z
2.0
—
2.0 — 2.0 — 2.0
—
ns
tKQHZ Clock High to Output High-Z
1.5 3.5
2 3.5 2 3.5 2
3.5
ns
tOEQ
Output Enable to Output Valid
—
5
—6—6—
6
ns
tOEQX Output Disable to Output Invalid 0
—
0—0—0
—
ns
tOELZ Output Enable to Output Low-Z
0
—
0—0—0
—
ns
tOEHZ Output Disable to Output High-Z —
3.5
— 3.5 — 3.5 —
3.5
ns
tAS
Address Setup Time
2.0
—
2.0 — 2.0 — 2.0
—
ns
tWS
Read/Write Setup Time
2.0
—
2.0 — 2.0 — 2.0
—
ns
tCES
Chip Enable Setup Time
2.0
—
2.0 — 2.0 — 2.0
—
ns
tSE
Clock Enable Setup Time
2.0
—
2.0 — 2.0 — 2.0
—
ns
tAVS
Address Advance Setup Time
2.0
—
2.0 — 2.0 — 2.0
—
ns
tAE
Address Hold Time
0.5
—
0.5 — 0.5 — 0.5
—
ns
tHE
Clock EnableHold Time
0.5
—
0.5 — 0.5 — 0.5
—
ns
tWH
Write Hold Time
0.5
—
0.5 — 0.5 — 0.5
—
ns
tCEH
Chip Enable Hold Time
0.5
—
0.5 — 0.5 — 0.5
—
ns
tALS
Advance/Load (ADV/LD) Setup Time2.0
—
2.0 — 2.0 — 2.0
—
ns
tALH
Advance/Load (ADV/LD) Hold Time 0.5
—
0.5 — 0.5 — 0.5
—
ns
tds
Data Setup Time
2.0
—
2.0 — 2.0 — 2.0
—
ns
tdh
Data Hold Time
0.5
—
0.5 — 0.5 — 0.5
—
ns
tzp
I/O From Tri-State to Valid
1.5
—
1.5 2.5 1.5 2.5 1.5 2.5
ns
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
Integrated Circuit Solution Inc.
11
SSR006-0B