IC-HT Datasheet, PDF (40/42 Pages) IC-Haus GmbH – DUAL CW LASER DIODE DRIVER

iC-HT
DUAL CW LASER DIODE DRIVER
preliminary
Channel 2 configuration registers
EACC2
0
1
Addr. 0x15; bit 0
R/W 0
APC mode enabled for channel 2 (light power
regulation)
ACC mode enabled for channel 2 (laser current
regulation)
Table 102: Enable APC/ACC channel 2
ECIE2
0
1
Addr. 0x15; bit 1
R/W 0
External CI capacitor for channel 2 disconnected
External CI capacitor for channel 2 connected
Table 103: Enable external CI capacitor channel 2
Rev A1, Page 40/42
RMD2
0x00
...
0xFF
Addr. 0x17; bit 7:0
R/W 0xFF
PLR2 resistor set to the minimum resistance
PLR2 resistor set to
Rmd
=
Rmd₀(1
+
∆
Rmd (%)
100
)ⁿ
+
1
,
n
from
0
to
255
PLR2 resistor set to the maximum resistance
Table 109: MDA resistor channel 2
COMP2
000
...
111
Addr. 0x18; bit 6:4
R/W 011
Minimum compensation current for the channel 2
regulator, slower response
Maximum compensation current for the channel 2
regulator, faster response
Table 110: Current compensation channel 2
DISP2
0
1
Addr. 0x15; bit 2
R/W 0
Internal resistor at MDA2 enabled for channel 2
Internal resistor at MDA2 disabled for channel 2
Table 104: Disable PLR channel 2
DISC2
0
1
Addr. 0x15; bit 3
Channel 2 can be enabled by EC2 pin
Channel 2 cannot be enabled by EC2 pin
R/W 1
Table 105: Disable channel 2
EOC2
0
1
Addr. 0x15; bit 4
R/W 1
Channel 2 regulator offset compensation disabled
Channel 2 regulator offset compensation enabled
Table 106: Enable offset compensation channel 2
RLDKS2
00
01
10
11
Addr. 0x18; bit 3:2
R/W 00
V(LDK2) < 0.5 V sets the LDKSAT2 alarm bit
V(LDK2) < 0.8 V sets the LDKSAT2 alarm bit
V(LDK2) < 1.0 V sets the LDKSAT2 alarm bit
V(LDK2) < 1.2 V sets the LDKSAT2 alarm bit
Table 111: LDK saturation threshold selection chan-
nel 2
REF2
0x000
...
0x3FF
Addr. 0x18/19; bit 9:0
R/W 0x000
Channel 2 regulator reference voltage set to
minimum voltage
Channel 2 regulator reference voltage set to
Vref
=
Vref₀(1
+
∆
Vref (%)
100
)ⁿ
+
1
,
n
from
0
to
1023
Channel 2 regulator reference voltage set to
maximum voltage
Table 112: Regulator voltage reference channel 2
ADCC2(2:0)
Addr. 0x15; bit 7:5
R/W 000
0xx
Channel 2 ADC disabled
100
Channel 2 ADC sourced by V(MDA2), ADSNF2 = 0
100
Channel 2 ADC sourced by V(PLR2), ADSNF2 = 1
101
Channel 2 ADC sourced by V(VB)
110
Channel 2 ADC sourced by V(VDD)
111
Channel 2 ADC sourced by V(LDK2)
Table 107: ADC source selection channel 2
ILIM2
0x00
...
0xFF
Addr. 0x16; bit 7:0
R/W 0xFF
Channel 2 overcurrent threshold set to the
minimum current
Channel 2 overcurrent threshold set to
Ilim = (∆ I(LDK ) · n), n from 0 to 255
Channel 2 overcurrent threshold set to the
maximum current
Table 108: Overcurrent threshold configuration chan-
nel 2
RACC1
0
1
Addr. 0x1A; bit 4
Current range high for channel 2
Current range low for channel 2
R/W 0
Table 113: Current range configuration channel 2
ADSNF2
0
1
Addr. 0x1A; bit 6
ADC measurement MDA2 pad (force)
ADC measurement PLR2 (sense)
R/W 0
Table 114: ADC channel 2 sense/force selection