IC-HT Datasheet, PDF (32/42 Pages) IC-Haus GmbH – DUAL CW LASER DIODE DRIVER

iC-HT
DUAL CW LASER DIODE DRIVER
preliminary
DIGITAL INTERFACE AND MEMORY INTEGRITY MONITOR
Rev A1, Page 32/42
iC-HT provides a microcontroller slave interface by se-
lection on the EMC pin. iC-HT support the interfaces
SPI or I²C that are selected by the INS/WKR pin.
ent registers) to be made prior to apply it to the laser
channels. iC-HT has two different modes selectable by
the MODE(1:0) register (addr. 0x1C).
EMC
lo
Open
hi
Addr. Pin;
iC-WK-mode, digital interfaces disabled
Not allowed, error signaled
MCU mode, interface selected by INS/WKR
enabled
Table 64: Enable microcontroller
INS/WKR
lo
Open
hi
Addr. Pin;
SPI interface selected
Not allowed, error signaled.
I²C interface selected
Table 65: Interface selection I²C or SPI
MODE(1:0)
Addr. 0x1C; bit 1:0
00
Invalid parameter
01
Operation mode
10
Configuration mode
11
Invalid parameter
R/W 01
Table 66: Configuration and operation mode
In Configuration mode, the configuration memory
(addr. 0x10 to 0x1F) can be written and read back to
check a correct communication without changing the
present configured operation state of the iC-HT. In this
mode, the memory integrity check is disabled.
The configuration memory is integrity monitored and
atomic executable (all at once: changes of the config-
urations without any direct effects, the changes are ex-
ecuted at once by command ) to the functional blocks
of iC-HT.
Integrity monitoring is implemented by a duplication of
the configuration registers into a validation page (see
description below) where the register are automatically
copied with inverted value. Every register bit is com-
pared with its validation copy and in case of difference,
a memory error is generated and both laser channels
are switched off.
Atomic appliance is achieved by latching the configu-
ration registers. This permits a full configuration (differ-
iC-HT will monitor the time elapsed in configuration
mode and automatically switch the laser off if it ex-
ceeds a configuration mode timeout. The time in con-
figuration mode must less than 40 ms for ensuring that
no configuration timeout occurs during configuration
(cf. Electrical Characteristics No. E02). The timeout
can be up to 164 ms.
When writing the configuration is completed, iC-HT is
switched to operation mode by writing "10" into the
MODE register (addr. 0x1C). In operation mode the
configuration is applied to the iC-HT and the memory
integrity check activated. In this mode configuration
registers can only be read (except MODE(1:0) regis-
ter, which is always accessible). Figure 18 shows the
interface to memory stucture.
CFG(127:0)
0x10
0x1F
RAM
MODE
Addr. 0x1C
LATCH
MEMERR
ERROR
CHECK
0x30
0x3F
VALIDATION
DB(7:0)
SPI / I2C
RNW
ADR(6:0)
Addr.
Decoder
RNW_RAM
RNW_VAL
Figure 18: Interface, RAM integrity monitoring and configuration latching