IC-NQL Datasheet, PDF (4/24 Pages) IC-Haus GmbH – 13-bit Sin/D CONVERTER WITH SSI INTERFACE

iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
PACKAGES TSSOP20 (according to JEDEC Standard)
Rev B1, Page 4/24
PIN CONFIGURATION
TSSOP20 4.4 mm, lead pitch 0.65 mm
PIN FUNCTIONS
No. Name Function
1 PCOS Input Cosine +
2 NCOS Input Cosine -
3 VDDA +5 V Supply Voltage (analog)
4 GNDA Ground (analog)
5 VREF Reference Voltage Output
6A
Incremental Output A
Analog signal COS+ (TMA mode)
PWM signal for Offset Sine (Calib.)
7B
Incremental Output B
Analog signal COS- (TMA mode)
PWM signal for Offset Cosine (Calib.)
8Z
Output Index Z
PWM signal for Phase/Ratio (Calib.)
9 GND Ground
10 VDD +5 V Supply Voltage (digital)
11 TEST Test Input
12 CLK SSI interface, clock line
13 DATA SSI interface, data output
14 SDA EEPROM interface, data line
Analog signal SIN+ (TMA mode)
15 SCL EEPROM interface, clock line
Analog signal SIN- (TMA mode)
16 NERR Error Input/Output, active low
17 PZERO Input Zero Signal +
18 NZERO Input Zero Signal -
19 PSIN Input Sine +
20 NSIN Input Sine -
External connections linking VDDA to VDD and GND to GNDA are required. The test input may remain unwired
or can be linked to VDD (please note the hints given by chapter Design Review regarding the signal of pin DATA).