IC-NQL Datasheet, PDF (10/24 Pages) IC-Haus GmbH – 13-bit Sin/D CONVERTER WITH SSI INTERFACE

iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
PARAMETERS and REGISTERS
Rev B1, Page 10/24
Register Description . . . . . . . . . . . . . . . . . . . . . . . Page 10
Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . Page 11
GAIN:
Gain Select
SINOFFS: Offset Calibration Sine
COSOFFS: Offset Calibration Cosine
REFOFFS: Offset Calibration Reference
RATIO:
Amplitude Calibration
PHASE:
Phase Calibration
Converter Function . . . . . . . . . . . . . . . . . . . . . . . . Page 12
SELRES: Resolution
HYS:
Hysteresis
FCTR:
Max. Permissible Converter Frequency
Incremental Signals . . . . . . . . . . . . . . . . . . . . . . . Page 15
CFGABZ: Output A, B, Z
ROT:
Direction of Rotation
CBZ:
Period Counter Configuration
ENRESDEL: Output Turn-On Delay
ZPOS:
CFGZ:
CFGAB:
Zero Signal Position
Zero Signal Length
Zero Signal Logic
Signal Monitoring
and Error Messages . . . . . . . . . . . . . . . . . . . . . . . Page 17
SELAMPL: Amplitude Monitoring, function
AMPL:
Amplitude Monitoring, thresholds
AERR:
Amplitude Error
FERR:
Frequency Error
Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 18
TMODE: Test Mode
TMA:
Analog Test Mode
SSI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 19
CFGTOS: Interface Timeout
M2S:
Period Counter Output
CFGSSI: SSI Output Options
OVERVIEW
Adr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x00
0
M2S(1:0)
SELRES(4:0)
0x01
HYS(2:0)
ZPOS(4:0)
0x02
ENRESDEL
1
ROT
CBZ
CFGABZ(1:0)
CFGZ(1:0)
0x03
CFGSSI(1:0)
CFGAB(1:0)
0
0
AERR
FERR
0x04
FCTR(7:0)
0x05
0
FCTR(14:8)
0x06
0
0
CFGTOS(1:0)
TMODE(2:0)
TMA
0x07
0
0
0
0
0
0
0
0
0x08
GAIN(3:0)
RATIO(3:0)
0x09
SINOFFS(7:0)
0x0A
COSOFFS(7:0)
0x0B
PHASE(5:0)
REFOFFS
RATIO(4)
0x0C
0
0
0
0
0
SELAMPL
AMPL(1:0)
0x0D
0
0
0
0
0
0
0
0
0x0E
0
0
0
0
0
0
0
0
0x0F
CRC(7:0) check sum over address 0x00-0x0E with CRC polynomial: "100100111" (read out of EEPROM)
Note
Registers not in use must be set to zero unless otherwise noted.
Table 5: Register layout