IC-NQC_11 Datasheet, PDF (25/29 Pages) IC-Haus GmbH – 13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION

iC-NQC
preliminary
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
BiSS
0x00
0x0F
0x10
0x1F
0x20
0x3F
0x40
0x41
0x42
0x43
0x44
0x47
0x48
0x77
0x78
0x7D
0x7E
0x7F
0x00
0x3F
n=0
RAM
0x00 Configuration
0x0F Data
Bank Selection ®n
0x78
0x7D
0x7E
0x7F
n=1
ROM
n=2
n=3
n = ...14
n = 15
EEPROM Bank 0
0x00 Configuration
0x0F Data
-16
0x10 unused
0x2F
0x30 not available
0x31 EDS Bank
0x32
Profile ID
0x33
0x34
Serial Number
0x37
0x38
Slave Register
0x67
0x68
Device ID
0x6D
0x6E
0x6F ^{Manufact. ID}
0x70
0x7F ^{not available}
Bank 1
0x80
0xBF
0xC0
Bank 2
0xFF
0x100
Bank 3
0x13F
...0x3FF Bank ...14
0x400
Bank 15
0x43F
not available
Figure 18: Registers and addressing
Rev D1, Page 25/29
Bank 0
R/W ---
0x41...0x7F
R/W R
Bank 1...7
R/W R
Bank 8...15
R/W R/W
RPL0 RPL1
Register
Protection
STARTUP BEHAVIOR
After the supply has been turned on (power on reset),
iC-NQC reads the configuration data from the EEP-
ROM and during this phase halts error pin NERR ac-
tively on a low signal (open drain output) as well as
data output SLO and the incremental signals at A, B
and Z on a high signal.
Only after a successful CRC the data output to SLO
and to the A, B, Z incremental outputs is released
and the error indication at pin NERR reset; an exter-
nal pull-up resistor can supply a high signal. iC-NQC
then switches to normal operation and determines the
current angle position, providing that a sensor is con-
nected up to it and there is no amplitude error (or this
is deactivated).
Should the CRC prove unsuccessful due to a data er-
ror (disrupted transmission, no EEPROM or the EEP-
ROM is not programmed), the configuration phase is
automatically repeated. After a third failed attempt, the
procedure is aborted and error pin NERR remains ac-
tive, displaying a permanent low.
So that it is always possible to configure the setup us-
ing the I/O interface - even without an EEPROM - iC-
NQC first ignores parameters TIMO, TOA and RPL.
The I/O interface can then be addressed in BiSS C
protocol with the longest timeout (30 µs maximum),
without safety settings being observed (cf. RPL =
0x0).This allows the configuration to be written to RAM
addresses 0x01 to 0x0C and to address 0x00. Ad-
dress 0x00 must be written to last of all and triggers an
internal reset (see description on page 20).
A short timeout of 3 µs maximum can be temporar-
ily activated by writing value 0x07 to address 0x7C
(address 124d) to keep the device configuration time
shorter.
When operated without an EEPROM, iC-NQC does
not respond to higher addresses - with the exception
of the BiSS addresses reserved for manufacturers and
device IDs (0x78 to 0x7F). This address area supplies
the chip version from the ROM.
After startup, iC-NQC does not recognize a defined
configuration; the configuration RAM can contain any
values.