IC-NQC_11 Datasheet, PDF (11/29 Pages) IC-Haus GmbH – 13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION

iC-NQC
preliminary
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
SIGNAL CONDITIONING
Rev D1, Page 11/29
Input stages SIN and COS are configured as instru-
mentation amplifiers. The amplifier gain must be se-
lected in accordance with the input signal amplitude
and programmed to register GAIN according to the fol-
lowing table. Half of the supply voltage is available at
VREF as a center voltage to enable the DC level to be
adapted.
GAIN
Code
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Adr 0x08, Bit 7:4
Amplification
80.000
66.667
53.333
40.000
33.333
28.571
26.667
20.000
14.287
10.000
8.000
6.667
5.333
4.000
3.333
2.667
Differential
up to 50 mVpp
up to 60 mVpp
up to 75 mVpp
up to 0.1 Vpp
up to 0.12 Vpp
up to 0.14 Vpp
up to 0.15 Vpp
up to 0.2 Vpp
up to 0.28 Vpp
up to 0.4 Vpp
up to 0.5 Vpp
up to 0.6 Vpp
up to 0.75 Vpp
up to 1 Vpp
up to 1.2 Vpp
up to 1.5 Vpp
Sine/Cosine Input Signal Levels Vin()
Amplitude
Average value (DC)
Single-ended
Differential
Single-ended
up to 100 mVpp
0.7 V ... VDDA - 1.2 V
0.8 V ... VDDA - 1.2 V
up to 120 mVpp
0.7 V ... VDDA - 1.2 V
0.8 V ... VDDA - 1.2 V
up to 0.15 Vpp
0.7 V ... VDDA - 1.2 V
0.8 V ... VDDA - 1.2 V
up to 0.2 Vpp
1.2 V ... VDDA - 1.2 V
1.3 V ... VDDA - 1.3 V
up to 0.24 Vpp
1.2 V ... VDDA - 1.2 V
1.3 V ... VDDA - 1.3 V
up to 0.28 Vpp
0.7 V ... VDDA - 1.2 V
0.8 V ... VDDA - 1.3 V
up to 0.3 Vpp
1.2 V ... VDDA - 1.2 V
1.3 V ... VDDA - 1.3 V
up to 0.4 Vpp
0.7 V ... VDDA - 1.2 V
0.8 V ... VDDA - 1.3 V
up to 0.56 Vpp
1.2 V ... VDDA - 1.3 V
1.4 V ... VDDA - 1.4 V
up to 0.8 Vpp
1.2 V ... VDDA - 1.3 V
1.4 V ... VDDA - 1.5 V
up to 1 Vpp
0.8 V ... VDDA - 1.4 V
1.0 V ... VDDA - 1.6 V
up to 1.2 Vpp
0.8 V ... VDDA - 1.4 V
1.1 V ... VDDA - 1.7 V
up to 1.5 Vpp
0.9 V ... VDDA - 1.5 V
1.3 V ... VDDA - 1.9 V
up to 2 Vpp
1.2 V ... VDDA - 1.6 V
1.7 V ... VDDA - 2.1 V
up to 2.4 Vpp
1.2 V ... VDDA - 1.7 V
1.8 V ... VDDA - 2.3 V
up to 3 Vpp
1.3 V ... VDDA - 1.8 V
2.0 V ... VDDA - 2.6 V
Table 6: Input gain
SINOFFS
COSOFFS
Code
0x00
0x01
...
0x7F
0x80
0x81
...
0xFF
Notes
Adr 0x09, Bit 7:0
Adr 0x0A, Bit 7:0
Output Offset
Input Offset
0V
0V
-7.8125 mV
-7.8125* mV / GAIN
...
...
-0.9922 V
-0.9922 V / GAIN
0V
0V
+7,8125 mV
+7.8125 mV / GAIN
...
...
+0.9922 V
+0.9922 V / GAIN
*) With REFOFFS = 0x00 and VDDA = 5 V.
Table 7: Sine/cosine offset calibration
REFOFFS
Code
0x00
0x01
Adr 0x0B, Bit 1
Reference Voltage
Dependent on VDDA
(example of application: MR sensors)
Not dependent on VDDA
(example of application: Sin/Cos encoders)
Table 8: Offset reference
RATIO
Code
0x00
0x01
...
0x0F
Adr 0x0B, Bit 0, Adr 0x08, Bit 3:0
COS / SIN
Code
COS / SIN
1.0000
0x10
1.0000
1.0067
0x11
0.9933
...
...
...
1.1
0x1F
0.9000
Table 9: Amplitude calibration
PHASE
Code
0x00
0x01
...
0x12
...
0x1F
Adr 0x0B, Bit 7:2
Phase Shift
90°
90.703125°
...
102.65625°
102.65625°
102.65625°
Code
0x20
0x21
...
0x32
...
0x3F
Phase Shift
90°
89.296875°
...
77.34375°
77.34375°
77.34375°
Table 10: Phase calibration