IC-NQC_11 Datasheet, PDF (20/29 Pages) IC-Haus GmbH – 13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION

iC-NQC
preliminary
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
NZB
Code
0
1
Notes
Adr 0x03, Bit 6
Function
Zero bit
No zero bit
The optional zero bit is output as the final bit after
the CRC.
Table 37: Zero bit
Rev D1, Page 20/29
SCD: Angle data with 8-bit period count
Bits
Type
Label
8
DATA
Period counter P(7:0)
13
DATA
Angle data S(12:0)
2
ERROR Error bits E1, E0
5
CRC
Polynomial 0x25
1
Zero
Zero bit
Config.
SELRES = 0x03, M2S = 0x01, CRC6 = 0, NZB = 0
ENCDS
Code
0x00
0x01
Adr 0x00, Bit 7
Description
Data output BiSS B or SSI
Data output BiSS C
Table 38: Protocol options
M2S can be used to set the number of period counter
bits sent as sensor data. The counter bits are trans-
mitted before the angle value, with the MSB leading.
The 5-bit CRC output is based on polynomial 0x25
(100101b), with the 6-bit CRC output based on poly-
nomial 0x43 (1000011b) automatically coming active
with longer SCD data, or when preselected by CRC6.
As a rule, CRC bits are sent inverted.
Table 40: Example format 2
SCD: Angle data with 24-bit period count
Bits
Type
Label
24
DATA
Period counter P(23:0)
13
DATA
Angle data S(12:0)
2
ERROR Error bits E1, E0
6
CRC
Polynomial 0x43 (no zero bit)
Config.
SELRES = 0x03, M2S = 0x03, CRC6 = 0, NZB = 1
Table 41: Example format 3
Register Communication
After the BiSS C protocol slave registers are directly
addressed in a reserved address area (0x40 to 0x7F).
Other storage areas are addressed dynamically and in
blocks. BiSS addresses 0x00 to 0x3F aim for a reg-
ister bank consisting of 64 bytes, the physical storage
address of which is determined by Bank Select n.
An additional zero bit can be output following the CRC
bits. However, disabling the zero bit by NZB = 1 is rec-
ommended when the output data length does not need
to comply with existing applications.
iC-NQC supports up to 16 storage banks, making it
possible to use an 8-bit EEPROM to its full capacity.
There is therefore also enough storage space for an
ID plate (EDS) and OEM data.
To obtain a position data output being compatible to the
BiSS B protocol parameter ENCDS = 0 does switch off
the CDS bit, without a replacement by a zero bit. Thus,
the output data length is shorten by one bit and register
communication is limited to the direction of the master
to the slave. The bidirectional BiSS C register commu-
nication must be enabled by setting ENCDS = 1.
Example Of BiSS Data Output
SCD: Angle data
Bits
Typ
Label
12
DATA
Angle data S(11:0)
2
ERROR Error nE and warning nW
6
CRC
Polynomial 0x43
Config.
SELRES = 0x04, M2S = 0x00, CRC6 = 1, NZB = 1
Table 39: Example format 1 for BiSS profile BP1
Information regarding memory map and addressing
via BiSS is given on page 25).
Internal Reset Function
A write access at RAM address 0x00 (BiSS address
0x00 with Bank Select n = 0) triggers an internal reset.
Based on the current configuration in the RAM, iC-
NQC restarts without reading the EEPROM. The con-
figured interface timeout and write protect settings be-
come active, the period counter is set to zero and any
stored configuration errors are deleted. The data out-
put via SLO and the incremental signals at A, B and Z
are released. Providing no amplitude error is present,
the converter again counts up from an angle value of
zero to the current angle position.
Short BiSS Timeout
For programming via the I/O interface iC-NQC has a
short BiSS timeout function according to the descrip-
tion of the BiSS C protocol (see page 19, Table 2, El.
Char. no. 6).