IC-GF Datasheet, PDF (21/26 Pages) IC-Haus GmbH – TRANSCEIVER

iC-GF
TRANSCEIVER
REGISTERS
Rev C1, Page 21/26
Configuration overview
The configuration bytes are readable and writeable,
with the exception of the IND bit (adr 0x00). The di-
agnostic register is read only. After reading, the bits
CFED, INITRAM and WUD are reset. The bits OVT,
OVL(1:0) and UVD(1:0) are set to high during the re-
spective error condition and stay high for least 35 ms
after the condition has been removed (Electrical Char-
acteristics Nos. 302, 405). Tables 27, 28 and 29 show
an overview of the registers, accessible in SPI mode.
Register Address Bits Default Description
DUTY
0x03 3:2
10 Duty cycle configuration for overload detection
ENCFD 0x02
7
0 Enable logging of changes at CFI
ENOD
0x01
0
1 Enable Open-Drain output at RX pin
ENPUD 0x01
3
1 Enable pull-up/down current at CFI pin
ENRND 0x02
4
1 Enable spread spectrum oscillator
ENSCR 0x02
6
0 Enable communication requests
FCFG
0x02 3:2
10 Filter configuration for TX and OEN
FCFI
0x02 1:0
01 Filter configuration for CFI
IND
0x00
7 R/O CFI status (independent of POL), r/o
INV
0x03 5:4
00 Switching channel inversion
INVPUD 0x01
1
0 Invert pull-up/down configuration at CFI
NEXC
0x03 1:0
11 Enable excitation current for capacitive loads
OEN
0x00 3:2
11 Switching channel enable
OUTD
0x00 1:0
00 Output data for the switching channels
POL
0x01
2
0 Polarity inversion at CFI
QCFG1 0x01 5:4
11 Switching channel 1 configuration
QCFG2 0x01 7:6
11 Switching channel 2 configuration
TXEN
0x00 5:4
01 Channel control select (register or pin)
SCR2
0x02
5
0 Communication request channel selection
Table 27: Overview of the configuration registers
Register Address Bits Description
INITR
0x04
0 Register reset
SCR
0x04
1 Communication request acknowledged
CFED
0x04
2 Change detection at CFI
OVT
0x04
3 Overtemperature
OVL(0)
0x04
4 Overload Channel 1
OVL(1)
0x04
5 Overload Channel 2
UVD(0) 0x04
6 Undervoltage VCC resp. VCC3
UVD(1) 0x04
7 Undervoltage VBO
Table 28: Overview of the diagnostic register (read only)
OVERVIEW
Adr
Bit 7
Bit 6
0x00
IND
0x01
QCFG2(1:0)
0x02
ENCFD
ENSCR
0x03
0x04
UVD(1:0)
Bit 5
Bit 4
TXEN(1:0)
QCFG1(1:0)
SCR2
ENRND
INV(1:0)
OVL(1:0)
Bit 3
Bit 2
OEN(1:0)
ENPUD
POL
FCFG(1:0)
DUTY(1:0)
OVT
CFED
Table 29: Register layout
Bit 1
Bit 0
OUTD(1:0)
INVPUD
ENOD
FCFI(1:0)
NEXC(1:0)
SCR
INITR