IC-GF Datasheet, PDF (18/26 Pages) IC-Haus GmbH – TRANSCEIVER

iC-GF
TRANSCEIVER
ttrig
tdead
TX
QNx
QPx
I(QNX)
Iexc()
Isc()
0
0
Isc()
Iexc()
I(QPx)
texc
Figure 9: Dynamic characteristic
Rev C1, Page 18/26
required – by means of register bit ENPUD (cf. Table
17).
POL
0
1
Adr 0x01; Bit (2)
R/W 0
CFI hi → RX hi (ENOD = 0) resp. on (ENOD = 1)
Pull-down current (ENPUD = 1, INVPUD = 0)
CFI hi → RX lo (ENOD = 0) resp. off (ENOD = 1)
Pull-up current (ENPUD = 1, INVPUD = 0)
Table 16: Input polarity
ENPUD
0
1
Adr 0x01; Bit (3)
CFI pull-up/down disabled
CFI pull-up/down enabled
Table 17: Enable pull-up/down
R/W 1
Feedback channel CFI–RX configuration
In SPI mode RX is a standard CMOS output, which
can also be configured as an open-drain output, using
the register bit ENOD (cf. Table 15).
The state of the CFI pin (high or low) is mapped inde-
pendent of POL to the register bit IND (see table 18).
Changes at CFI can be logged in the status bit CFED
(and signalled at pin NDIAG), if the bit ENCFD is set to
high. The CFED bit is cleared after read.
ENOD
0
1
Adr 0x01; Bit (0)
Push-pull output
Open-drain output
Table 15: RX configuration
R/W 1
The polarity of the feedback channel CFI–RX can be
configured using register bit POL (cf. Table 16). Pin
CFP has no function in SPI mode. The POL bit also
controls the pull-up/down current at CFI. The INVPUD
bit changes the polarity of the pull-up/down current at
CFI independent of the other configurations. The pull-
up/down current can be disconnected completely – if
IND
Adr 0x00; Bit (7)
R
0
Input Signal at CFI is low
1
Input Signal at CFI is high
Table 18: CFI status
ENCFD
0
1
Adr 0x02; Bit (7)
CFED Disabled
CFED Enabled
R/W 0
Table 19: Enable edge detection at CFI
Table 20 summarizes the behaviour of the feedback
channel CFI in SPI mode.
Feedback channel CFI
CFI POL INVPUD IND RX (ENOD = 0) RX (ENOD = 1) Current at CFI
00
0
0
0
off
down
10
0
1
1
on
down
01
0
0
1
on
up
11
0
1
0
off
up
00
1
0
0
off
up
10
1
1
1
on
up
01
1
0
1
on
down
11
1
1
0
off
down
Table 20: Function table of feedback channel CFI in SPI mode (ENPUD = 1)
Overload detection
In SPI mode the counter decrements of the overload
detection can be programmed with the register DU-
TYC(1:0), resulting in different overload duty cycles at
the switching channels. The maximum allowed over-