HY62UF16806B Datasheet, PDF (9/11 Pages) Hynix Semiconductor – 512Kx16bit full CMOS SRAM

DATA RETENTION TIMING DIAGRAM 1
VCC
2.7V
VIH
VDR
/CS1
VSS
DATA RETENTION MODE
tCDR
tR
CS1>VCC-0.2V
DATA RETENTION TIMING DIAGRAM 2
VCC
2.7V
CS2
DATA RETENTION MODE
tCDR
tR
VDR
0.4V
VSS
CS2<0.2V
HY62UF16806B
Rev.01/Mar. 2002
8