HY62UF16806B Datasheet, PDF (6/11 Pages) Hynix Semiconductor – 512Kx16bit full CMOS SRAM

HY62UF16806B
TIMING DIAGRAM
READ CYCLE 1(Note 1,4)
ADDR
/CS1
tRC
tAA
tOH
tACS
CS2
tBA
/UB ,/ LB
/OE
Data
Out
High-Z
tOE
tOLZ(3)
tBLZ(3)
tCLZ(3)
READ CYCLE 2(Note 1,2,4)
ADDR
Data
Out
tRC
tAA
tOH
Previous Data
READ CYCLE 3(Note 1,2,4)
tCHZ(3)
tBHZ(3)
tOHZ(3)
Data Valid
tOH
Data Valid
/CS1
/UB, /LB
CS2
tACS
tCLZ(3)
tCHZ(3)
Data
Out
Data Valid
Notes:
1. Read Cycle occurs whenever a high on the /WE and /OE is low, while /UB and/or /LB and /CS1 and
CS2 are in active status.
2. /OE = VIL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS1 in high for the standby, low for active
CS2 in low for the standby, high for active. /UB and /LB in high for the standby, low for active
Rev.01/Mar. 2002
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