HY5V66EF6 Datasheet, PDF (9/12 Pages) Hynix Semiconductor – 64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O

11Preliminary
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY5V66E(L)F6(P) Series
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter
5
6
7
H
P
Symbol
Unit Note
Min Max Min Max Min Max Min Max Min Max
System Clock
Cycle Time
CAS
Latency=3
tCK3
CAS
Latency=2
tCK2
5.0
6.0
7.0
7.5
10
ns
1000
1000
1000
1000
1000
10
10
10
10
10
ns
Clock High Pulse Width
tCHW
2.0 - 2.5 - 3.0 - 3.0 - 3.0 - ns 1
Clock Low Pulse Width
tCLW
2.0 - 2.5 - 3.0 - 3.0 - 3.0 - ns 1
Access Time
From Clock
CAS
Latency=3
tAC3
CAS
Latency=2
tAC2
- 4.5 - 5.5 - 5.5 - 5.5 - 5.5 ns
2
- 6.0 - 6.0 - 6.0 - 6.0 - 6.0 ns
Data-out Hold Time
tOH
2.0 - 2.0 - 2.0 - 2.0 - 2.0 - ns
Data-Input Setup Time
tDS
1.5 - 1.5 - 1.5 - 1.5 - 2.0 - ns 1
Data-Input Hold Time
tDH
0.8 - 0.8 - 0.8 - 0.8 - 1.0 - ns 1
Address Setup Time
tAS
1.5 - 1.5 - 1.5 - 1.5 - 2.0 - ns 1
Address Hold Time
tAH
0.8 - 0.8 - 0.8 - 0.8 - 1.0 - ns 1
CKE Setup Time
tCKS
1.5 - 1.5 - 1.5 - 1.5 - 2.0 - ns 1
CKE Hold Time
tCKH
0.8 - 0.8 - 0.8 - 0.8 - 1.0 - ns 1
Command Setup Time
tCS
1.5 - 1.5 - 1.5 - 1.5 - 2.0 - ns 1
Command Hold Time
tCH
0.8 - 0.8 - 0.8 - 0.8 - 1.0 - ns 1
CLK to
Time
Data
Output
in
Low-Z
tOLZ
1.0 - 1.0 - 1.5 - 1.5 - 2.0 - ns
CLK to
Data Output
in High-Z Time
CAS
Latency=3
tOHZ3
CAS
Latency=2
tOHZ2
- 4.5 - 5.5 - 5.5 - 6.0 - 6.0 ns
- 6.0 - 6.0 - 6.0 - 6.0 - 6.0 ns
Note :
1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.
2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns,
then (tR/2-0.5)ns should be added to the parameter.
Rev. 0.2 / June. 2005
9