HY5V66EF6 Datasheet, PDF (10/12 Pages) Hynix Semiconductor – 64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O

11Preliminary
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY5V66E(L)F6(P) Series
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
Parameter
5
6
7
H
P
Symbol
Unit Note
Min Max Min Max Min Max Min Max Min Max
RAS
Cycle Time
Operation _tRC
55 - 60 - 63 - 63 - 70 - ns
RAS
Cycle Time
Auto Refresh _tRRC
55 - 60 - 63 - 63 - 70 - ns
RAS to CAS Delay
tRCD
15 - 18 - 20 - 20 - 20 - ns
RAS Active Time
tRAS
38.7 100K
42
100K
42
100K
42
120
K
50
120
K
ns
RAS Precharge Time
tRP
15 - 18 - 20 - 20 - 20 - ns
RAS to RAS Bank Active
Delay
tRRD
20 - 20 - 20 - 20 - 20 - ns
CAS to CAS Delay
tCCD
1 - 1 - 1 - 1 - 1 - CLK
Write Command to
Data-In Delay
tWTL
0 - 0 - 0 - 0 - 0 - CLK
Data-in to Precharge
Command
tDPL
2 - 2 - 2 - 2 - 2 - CLK
Data-In to Active Command tDAL
DQM to Data-Out Hi-Z
tDQZ
tDPL + tRP
2 - 2 - 2 - 2 - 2 - CLK
DQM to Data-In Mask
tDQM
0 - 0 - 0 - 0 - 0 - CLK
MRS to New Command
tMRD
2 - 2 - 2 - 2 - 2 - CLK
Precharge to
Data Output
High-Z
CAS
Latency=3
CAS
Latency=2
tPROZ3
tPROZ2
3-3-
2-2-
3 - 3 - 3 - CLK
2 - 2 - 2 - CLK
Power Down Exit Time
tDPE
1 - 1 - 1 - 1 - 1 - CLK
Self Refresh Exit Time
tSRE
1 - 1 - 1 - 1 - 1 - CLK 1
Refresh Time
tREF
- 64 - 64 - 64 - 64 - 64 ms
Note :
1. A new command can be given tRRC after self refresh exit.
Rev. 0.2 / June. 2005
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