GDC21D401B Datasheet, PDF (9/28 Pages) Hynix Semiconductor – Video Decoder

4. Block Diagram
GDC21D401B
27 MHz System Clock
Display Sync
I 2C I/F
Video
Bitstream
Video
Bitstream
Pre-
decoder
FIFO
STC
DTS check
Decoding
Controller
Sequence
Parcer
FIFO
IDCT
Coefficient
Decoder
Quantization
Matrix
IDCT
coefficients
IIQQ
&&
BBuuffffeerr
Macroblock
Parameter
Decoder
MB
parameters
MB
Decoding
Controller
Max.200 M sample/sec
High-Speed IDCT
32
IIDDCCTT
Predictor
FIFO
Decoded
MB Data
Display
Processor
Control
32
Data
Window
Motion
Vector
Decoder
MB
Motion
Vector
MV
Processor
64
Internal Data Bus
SDRAM
Controller
Half- pel
Predictor
FIFO
Figure 2. MPEG-2 MP@HL Video Decoder Block Diagram
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