GDC21D401B Datasheet, PDF (15/28 Pages) Hynix Semiconductor – Video Decoder

GDC21D401B
Interrupt Mechanism
The host enables specific interrupt events to occur
by setting the mask value of internal interrupt.
When an event occurs and corresponding interrupt
enable is set, an interrupt bit is set in an interrupt
register. Everytime each picture decodes sync, host
checks the contents of that register, and if any bit
is set, it generates an interrupt. Exceptionally, in
the case of OVF, UND and ERR interrupt signals
are generated as soon as the error is detected.
When the host serves the interrupt, interrupt
register and interrupt signal are reset.
Table 2. Bit Definitions for Interrupt Register & Mask
BIT #
0
1
2
3
4
MNEMONIC
EVENT
PIC_S
Picture decoding
GOP_H
GOP header decoding
SEQ_H
Seq. header decoding
SEQ_E
Seq. end decoding
USR
User data ready
5 OVF
6 UND/PTS
Buffer overflow
Buffer underflow/
PTS received
7 ERR
Bitstream error
EVENT DEFINITION
New picture is decoded.
GOP headers are decoded.
Sequence headers are decoded.
Sequence end code is decoded.
User data has been extracted and stored in the buffer. When
the interrupt is disabled, user data is discarded.
Bitstream buffer is full.
Dec_mode(4) = ‘0’:
Bitstream buffer doesn’t have 1 picture bitstream.
Dec_mode(4) = ‘1’
PTS value is received through transport interface.
Error code or syntax error is detected in the bitstream
(header layer).
16