GDC21D401B Datasheet, PDF (20/28 Pages) Hynix Semiconductor – Video Decoder

5.15 Video Data Output Timing
During decoding the picture which is field picture
or frame picture, PDWIN signal is high. Between
each picture decoding time, there is low level
period of PDWIN signal, and it is longer than 128
VDCLKs. Picture parameter such as PSTR[1:0] or
\FFPN is determined 2 clocks before PDWIN
GDC21D401B
rising edge. Its value is not changed until PDWIN
falling edge. SCLK shows that new slice decoding
is started on its rising edge. Width of MBCLK
high pulse is always 96 clocks, and low value
period is longer than 2 clocks.
PDWIN
PSTR[1:0]
\FFPN
SCLK
2 VDCLKs
Minimum
1 VDCLK
SCLK
MBCLK
MBFI
PDATA[31:0]
VDCLK
0123
Minimum
128 VDCLKs
94 95
Figure 9. Timing Diagram
21