GDC21D401B Datasheet, PDF (6/28 Pages) Hynix Semiconductor – Video Decoder

GDC21D401B
(Package: 240 HQFP)
NAME
PIN
VDCLK
165
MCLK
94
MCLK_IN
234
MCLK_OUT
237
CLK_27M
6
\RESET
8
SCL
SDA
VID_DATA[7:0]
\VID_REQ
VID_STRB
TSW
26
28
25,23,21,20,
18,16,15,14
29
13
9
\VIDEN
10
VSTCW
11
\INT_V
31
\UBUFF_FULL
30
CSN
WEN
RASN
CASN
BA0
SDRAM_ADDR
[10:0]
SDRAM_DATA
[63:0]
109
106
108
107
104
103,102,101,
99,92,89,86,
84,87,91,98
163,162,161,
158,157,154,
152,150,43,
42,40,39,38,
36, 34, 33
TYPE
DESCRIPTION
CLOCK
I
Operating clock. - 54 MHz (max), 50 % duty cycle
I
SDRAM interface clock. - 81 MHz (max), 50 % duty cycle
I
SDRAM interface clock. - 81 MHz (max),
50 % duty cycle (the same clock as MCLK)
O
SDRAM interface clock through clock buffer for delay effect.
This signal input is MCLK_IN.
I
External system time clock. - 27 MHz
RESET
I
Power on reset(active low). At least 3 VDCLKs.
Decoding starts after 128 VDCLKs from the last reset low state.
I²C-BUS INTERFACE
I
I²C-bus serial clock. - 400 KHz(max)
I/O I²C-bus serial data
TRANSPORT INTERFACE
I
Transport Decoder data bus
O
Transport data request(active low)
I
Transport data strobe.
VID_DATA[7:0] is latched on the rising edge.
I
PTS & DTS data enable(active high).
In LG DTV chipset, this signal is connected to the
PTS_DTS_STRB pin of GDC21D301A.
I
Video bitstream data enable(active low)
I
STC data enable(active high)
HOST INTERRUPT
O
Video decoder interrupt(active low)
O
User data FIFO is full(active low).
When it happens, host microprocessor must read the user data
from user data FIFO.
Otherwise video decoder suspends decoding.
SDRAM INTERFACE
O
SDRAM chip selection(active low)
O
SDRAM write enable(active low)
O
SDRAM row address selection(active low)
O
SDRAM column address selection(active low)
O
SDRAM bank address.
This indicates bank address, and low value selects bank ‘0’.
O
SDRAM address
I/O SDRAM data bus
7