GDC21D401B Datasheet, PDF (18/28 Pages) Hynix Semiconductor – Video Decoder

BIT #
0
1
2
3
4
5~7
GDC21D401B
Table 6. Definition of Decoding Mode Register
DESCRIPTION
It must have “High”.
DTS input timing: ‘0’ => DTS values are transferred to VD before the associated PSTC.
‘1’ => DTS values are transferred to VD after the associated PSTC.
PSTC represents the Picture Start Code.
DTS synchronization: ‘0’ => disabled ‘1’ => enabled
Picture reordering in VBV delay mode: ‘0’ => enabled ‘1’ => disabled
Int_reg(6) & Int_mask(6) selection: ‘0’ => UND ‘1’ => PTS
“000” : Not used
19