HYMP512R72L Datasheet, PDF (8/18 Pages) Hynix Semiconductor – DDR2 SDRAM Registered DIMM

Input AC Logic Level
HYMP512R72(L)4
Parameter
AC Input logic High
AC Input logic Low
Symbol
VIH(AC)
VIL(AC)
AC Input Test Conditions
Min
VREF + 0.250
-
Max
-
VREF - 0.250
Unit
Note
V
V
Symbol
V_REF
V_SWING(MAX)
SLEW
Condition
Input reference voltage
Input signal maximum peak to peak swing
Input signal minimum slew rate
Value
0.5 * V_DDQ
1.0
1.0
Units
V
V
V/ns
Notes
1
1
2, 3
Notes:
1. Input waveform timing is referenced to the input signal crossing through the V_REF level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from V_IL(dc) max to V_IH(ac) min for rising edges and the
range from V_IH(dc) min to V_IL(ac) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to
VIL(ac) on the negative transitions.
Start of Falling Edge Input Timing
V_SWING(MAX)
delta TF
Falling Slew = ^{VIH(dc) min - VIL(ac) max}
delta TF
Start of Rising Edge Input Timing
delta TR
V_DDQ
V_IH(ac) min
V_IH(dc) min
V_REF
V_IL(dc) max
V_IL(ac) max
V_SS
Rising Slew = ^{VIH(ac) min - VIL(dc) max}
delta TR
< Figure : AC Input Test Signal Waveform >
Rev. 0.2 / July 2004
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