HYMP512R72L Datasheet, PDF (14/18 Pages) Hynix Semiconductor – DDR2 SDRAM Registered DIMM

HYMP512R72(L)4
- continued -
Parameter
Address and control input hold time
Address and control input setup time
Read preamble
Read postamble
Auto-Refresh to Active/Auto-Refresh
command period
Row Active to Row Active Delay
CAS to CAS command delay
Write recovery time
Auto Precharge Write Recovery + Precharge
Time
Write to Read Command Delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
Exit precharge power down to any non-read
command
Exit active power down to read command
Exit active power down to read command
(Slow exit, Lower power)
CKE minimum pulse width
(high and low pulse width)
ODT turn-on delay
ODT turn-on
ODT turn-on(Power-Down mode)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down mode)
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
Minimum time clocks remains ON after
CKE asynchronously drops LOW
Average periodic Refresh Interval
Symbol
tIH
tIS
tRPRE
tRPST
tRFC
DDR2 400
Min
Max
600
-
600
-
0.9
1.1
0.4
0.6
105
-
DDR2 533
Min
Max
500
-
500
-
0.9
1.1
0.4
0.6
105
-
DDR2 667
Min
Max
tbd
-
tbd
-
0.9
1.1
0.4
0.6
105
-
Unit Note
ps
ps
tCK
tCK
ns
tRRD
7.5
-
7.5
-
7.5
-
ns
tCCD
2
2
2
tCK
tWR
15
-
15
-
15
-
ns
(tWR/tCK)
(tWR/tCK)
(tWR/tCK)
tDAL
+
-
+
-
+
-
tCK
(tRP/tCK)
(tRP/tCK)
(tRP/tCK)
tWTR
10
-
7.5
-
7.5
-
ns
tRTP
7.5
7.5
7.5
ns
tXSNR tRFC + 10
tRFC + 10
tRFC + 10
ns
tXSRD
200
-
200
-
200
-
tCK
tXP
2
-
2
-
2
-
tCK
tXARD
2
2
2
tCK
tXARDS 6 - AL
6 - AL
6 - AL
tCK
t_CKE
3
3
3
tCK
t_AOND
2
2
2
2
2
2
tCK
t_AON
tAC(min)
tAC(max)
+1
tAC(min)
tAC(max)
+1
tAC(min)
tAC(max)
+0.7
ns
t_AONPD
tAC(min)+2
2tCK+tAC
(max)+1
tAC(min)+2
2tCK+tAC
(max)+1
tAC(min)+2
2tCK+tAC
(max)+1
ns
t_AOFD
2.5
2.5
2.5
2.5
2.5
2.5
tCK
t_AOF
tAC(min)
tAC(max)
+ 0.6
tAC(min)
tAC(max)
+ 0.6
tAC(min)
tAC(max)
+ 0.6
ns
t_AOFPD
tAC(min)+
2
2.5tCK+t
AC(max)
+1
tAC(min)+
2
2.5tCK+t
AC(max)
+1
tAC(min)+
2
2.5tCK+t
AC(max)
+1
ns
tANPD
3
3
3
tCK
tAXPD
8
8
8
tCK
tOIT
0
12
0
12
0
12
ns
tDelay
tIS+tCK+tI
H
tIS+tCK+tI
H
tIS+tCK+tI
H
ns
tREFI
-
7.8
-
7.8
-
7.8 us 2
tREFI
-
3.9
-
3.9
-
3.9
us
3
Note :
1. For details and notes, please refer to the relevant HYNIX component datasheet(HY5PS12821(L)F).
2. 0°C ≤ TCASE ≤ 85°C
3. 85°C ＜ TCASE ≤ 95°C
Rev. 0.2 / July 2004
14