HYMP512R72L Datasheet, PDF (4/18 Pages) Hynix Semiconductor – DDR2 SDRAM Registered DIMM

PIN DESCRIPTION
Pin
Pin Description
CK0
Clock Input,positive line
CK0
Clock input,negative line
CKE0~CKE1 Clock Enable Input
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
S0
Chip Select Input
A0~A9,A11~A13 Address input
A10/AP
Address input/Autoprecharge
BA0, BA1
SDRAM Bank Address
SCL
Serial Presence Detect(SPD) Clock Input
SDA
SA0~SA2
Par_In
Err_Out
RESET
CB0~CB7
SPD Data Input/Output
E²PROM Address Inputs
Parity bit for the Address and Control bus
Parity error found on the Addre
Reset Enable
Data Strobe Inputs/Outputs
PIN Location
HYMP512R72(L)4
Pin
Pin Description
ODT[1:0]
On Die Termination Inputs
VDDQ
DQs Power Supply
DQ0~DQ63
Data Input/Output
CB0~CB7
Data check bits Input/Output
DQS(0~8)
Data strobes
DQS(0~8)
Data strobes,negative line
DM(0~8),DQS(9~17) Data Maskes/Data strobes
DQS(9~17)
Data strobes,negative line
RFU
Reserved for Future Use
NC
No Connect
TEST
Memory bus test tool(Not Connected and Not
Usable on DIMMs)
VDD
Core Power
VDDQ
I/O Power Supply
VSS
VREF
VDDSPD
Ground
Reference Power Supply
Power Supply for SPD
Front Side
1 pin
64 pin 65 pin
121 pin
Back Side ^{184 pin 185 pin}
120 pin
240 pin
Rev. 0.2 / July 2004
4