HYMP512R72L Datasheet, PDF (13/18 Pages) Hynix Semiconductor – DDR2 SDRAM Registered DIMM

HYMP512R72(L)4
Electrical Characteristics & AC Timings
Speed Bins and CL,tRCD,tRP,tRC and tRAS for Corresponding Bin
Speed
Bin(CL-tRCD-tRP)
Parameter
CAS Latency
tRCD
tRP
tRC
tRAS
DDR2-667(Y5)
5-5-5
min
5
15
15
55
40
DDR2-667(Y6)
6-6-6
min
6
18
18
63
45
DDR2-533(C4)
4-4-4
min
4
15
15
60
45
DDR2-533(C5) DDR2-400(C3) DDR2-400(C4) Unit
5-5-5
3-3-3
4-4-4
min
min
min
5
3
4
ns
18.75
15
20
ns
18.75
15
20
ns
63.75
55
65
ns
45
40
45
ns
AC Timing Parameters by Speed Grade
Parameter
Symbol
DDR2-400
Min
Max
DDR2-533
Min
Max
DDR2-667
Min
Max
Unit Note
Data-Out edge to Clock edge Skew
tAC
-600
600
-500
500
-450
450
ps
DQS-Out edge to Clock edge Skew
tDQSCK -500
500
-500
450
-400
400
ns
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
0.45
0.55 CK
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
0.45
0.55 CK
Clock Half Period
tHP
min
(tCL,tCH)
-
min
(tCL,tCH)
-
min
(tCL,tCH)
-
ns
System Clock Cycle Time
tCK
5000
8000
3750
8000
3000
8000 ps
DQ and DM input hold time
tDH
400
-
350
-
300
-
ps
1
DQ and DM input setup time
tDS
400
-
350
-
300
-
ps
1
Control & Address input Pulse Width for each input tIPW
0.6
-
0.6
-
0.6
-
tCK
DQ and DM input pulse witdth for each input pulse
width for each input
tDIPW
0.35
-
0.35
-
0.35
-
tCK
Data-out high-impedance window from CK, /CK
tHZ
-
tAC max
-
tAC max
-
tAC max ps
DQS low-impedance time from CK/CK
tLZ(DQS) tAC min tAC max tAC min tAC max tAC min tAC max ps
DQ low-impedance time from CK/CK
tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max 2*tAC min tAC max ps
DQS-DQ skew for DQS and associated DQ signals tDQSQ
-
350
-
300
-
tbd
ps
DQ hold skew factor
tQHS
-
450
-
400
-
tbd
ps
DQ/DQS output hold time from DQS
tQH tHP - tQHS - tHP - tQHS - tHP - tQHS -
ps
Write command to first DQS latching transition
tDQSS WL - 0.25 WL + WL - 0.25 WL + WL - 0.25 WL + tCK
0.25
0.25
0.25
DQS input high pulse width
tDQSH
0.35
-
0.35
-
0.35
-
tCK
DQS input low pulse width
tDQSL
0.35
-
0.35
-
0.35
-
tCK
DQS falling edge to CK setup time
tDSS
0.2
-
0.2
-
0.2
-
tCK
DQS falling edge hold time from CK
tDSH
0.2
-
0.2
-
0.2
-
tCK
Mode register set command cycle time
tMRD
2
-
2
-
2
-
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write preamble
tWPRE
0.35
-
0.35
-
0.35
-
tCK
Rev. 0.2 / July 2004
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