HY51VS65163HG Datasheet, PDF (8/11 Pages) Hynix Semiconductor – 4M x 16Bit EDO DRAM

HY51V(S)65163HG/HGL
Extended Data Out Mode Cycles
Parameter
EDO page mode cyle time
Write pulse width during /CAS precharge
EDO mode /RAS pulse width
Access time from /CAS precharge
/RAS hold time from /CAS precharge
/CAS hold time referred /OE
/CAS to /OE set-up time
Read command hold time
from /CAS precharge
Output data hold time from /CAS low
/OE precharge time
Symbol
tHPC
tWPE
tRASP
tACP
tRHCP
tCOL
tCOP
-45
Min Max
17
-
7
-
-
100K
-
28
26
-
7
-
5
-
-50
Min Max
20
-
8
-
-
100K
-
28
28
-
8
-
5
-
-60
Unit Note
Min Max
25
-
ns 25
10
-
ns
-
100K ns 16
-
35
ns 9,17,22
35
-
ns
10
-
ns
5
-
ns
tRCHP
26
-
28
-
35
-
ns
tDOH
3
-
3
-
3
-
ns 9,27
tOEP
7
-
8
-
10
-
ns
EDO Page Mode Read-Modify-Write Cycle
Parameter
EDO read-modify-write cycle time
EDO page mode read-modify-write cycle
/CAS precharge to /WE delay time
Symbol
tHPRWC
-45
Min Max
57
-
tCPW
45
-
-50
Min Max
57
-
45
-
-60
Unit Note
Min Max
68
-
ns
54
-
ns 14,22
Self Refresh Cycle (L-Version)
Parameter
/RAS pulse width ( self refresh)
/RAS precharge time ( self refresh)
/CAS hold time ( self refresh)
Symbol
tRASS
tRPS
tCHS
-45
Min Max
100
-
90
-
-50
-
-50
Min Max
100
-
90
-
-50
-
-60
Unit Note
Min Max
100
-
us 31
110
-
ns 31
-50
-
ns 23
Rev 0.1 / Apr. 01