HY51VS65163HG Datasheet, PDF (10/11 Pages) Hynix Semiconductor – 4M x 16Bit EDO DRAM

HY51V(S)65163HG/HGL
19. When output buffers are enabled once, sustain the low impedence state until valid data is obtained.
when output buffer is turned on and off within a very short time, generally it causes large Vcc/Vss line
noise, which causes to degrade VIH min / VIL max level
20. When both /UCAS and /LCAS go low at the same time, all 16 bit data are written into the device.
/UCAS and /LCAS cannot be staggered within the same write / read cycles
21. tASC, tCAH, tRCS, tWCS, tWCH, tCSR and tRPC are determined by the earlier falling edge of /UCAS or /LCAS
22. tCRP, tCHR, tRCH,tACP and tCPW are determined by the later rising edge of /UCAS or /LCAS
23. tCWL, tDH, tDS and tCHS should be satified by the both /UCAS and /LCAS
24. tCP is determined by the time that both /UCAS and /LCAS are high
25. tHPC(min) can be achieved during a series of EDO mode early write cycles or EDO mode read cycels
If both write and read operation are mixed in a EDO mode, /RAS cycle[EDO mode mix cycle (1)(2)]
minimum value of /CAS cycle tHPC[tCAS + tCP + 2tT] become greater than the specified tHPC(min)
value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle
(1) and (2)
26. Data output turns off and becomes high impedance from later rising edge of /RAS and /CAS.
Hold time and turn off time are specified by the timing specifications of later rising edge of /RAS and
/CAS between tOHR and tOH and between tOFR and tOFF
27. tDOH defines the time at which the output level go cross, VOL=0.8V, VOH=2.0V of output timing
reference level.
28. Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64ms
period on the condition a) and b) below
a) Enter self refresh mode within 15.6us after either burst refresh or distributed refresh at equal interval
to all refresh addresses are completed.
b) Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6us after
exiting from self refresh mode
29. In case of entering from /RAS-only-refresh, It is necessary to execute CBR refresh before and after
self refresh mode according as note 28
30. For L-version, It is available to apply each 128ms and 31.2us instead of 64ms and 15.6us at note 28
31. At tRASS > 100us, self refresh mode is activated, and not active at tRASS < 10us, It is undefined within
the range of 10us < tRASS < 100us. For tRASS > 10us, It is necessary to satify tRPS
32. XXX : H or L [ H : VIH(min) <= VIN <=VIH(max), L : VIH(min) <=VIN <=VIH(max)]
///// : Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must be
applied VIH or VIL
Rev 0.1 / Apr. 01