HY51VS65163HG Datasheet, PDF (4/11 Pages) Hynix Semiconductor – 4M x 16Bit EDO DRAM

HY51V(S)65163HG/HGL
DC CHARACTERISTICS (Vcc = 3.3V +/- 10%, TA=0 to 70°C)
Symbol
Parameter
VOH
Output Level
Output Level voltage(Iout= -2mA)
VOL
Output Level
Output Level voltage(Iout=2mA)
45ns
ICC1 Operating current ( tRC = tRC min)
50ns
60ns
ICC2
Standby current (TTL interface)
Power supply standby current
(/RAS, /UCAS,/LCAS=VIH, Dout = High-Z)
45ns
ICC3 /RAS only refresh current (tRC= tRC min)
50ns
60ns
45ns
Extended data out page mode current
ICC4 _{(/RAS=VIL, /CAS, Address cycling : tHPC=tHPC min)}
50ns
60ns
CMOS interface ( /RAS, /UCAS, /LCAS >= Vcc-0.2V, Dout = High-Z)
ICC5
Standby current ( L-version)
45ns
ICC6 /CAS-before-/RAS refresh current (tRC=tRC min)
50ns
60ns
ICC7
Battery back up operating current (standby with CBR)
(tRC=31.25us, tRAS=300ns, Dout=High-Z)
ICC8
Standby current (CMOS)
Power supply standby current
/RAS=VIH, /UCAS./LCAS=VIL, Dout=Enable)
ICC9
Self refresh current
(/RAS, /UCAS, /LCAS <=0.2V, Dout=High-Z)
II(L) Input leakage current, Any input (0V<= Vin<=Vcc)
IO(L) Output leakage current, (Dout is disabled, 0V<= Vout<=Vcc)
Min Max Unit
2.4
Vcc
V
0
0.4
V
-
130
-
120
mA
-
110
-
1
mA
-
130
-
120
mA
-
110
-
100
-
90
mA
-
80
-
0.5
mA
-
200
uA
-
130
-
120
mA
-
110
-
350
uA
-
5
mA
-
350
uA
-5
5
uA
-5
5
uA
Note :
1. Icc depends on output load condition when the device is selected, Icc(max) is specified at the output open condition
2. Address can be changed once or less while RAS=VIL
3. Measured with one sequential address change per EDO cycle, tHPC
4. VIH>=Vcc-0.2V, 0V<=VIL<=0.2V
5. L-Version
Note
1, 2
2
1, 3
4
4, 5
1
5
Rev.0.1/Apr.01
4