GMS81C2020 Datasheet, PDF (71/92 Pages) Hynix Semiconductor – CMOS Single-Chip 8-Bit Microcontroller with A/D Converter & VFD Driver

Hyundai Micro Electronics
GMS81C2020/GMS81C2120
19.4 External Interrupt
The external interrupt on INT0 and INT1 pins are edge
triggered depending on the edge selection register IEDS
(address 0E6_H) as shown in Figure 19-6 .
The edge detection of external interrupt has three transition
activated mode: rising edge, falling edge, and both edge.
INT0 pin
INT1 pin
INT0IF
INT0 INTERRUPT
INT1IF
INT1 INTERRUPT
Example: To use as an INT0, INT1
:
:
;**** Set port as an input port R00,R01
LDM R0IO,#1111_1100B
;
;**** Set port as an interrupt port
LDM R0FUNC,#03H
;
;**** Set Falling-edge Detection
LDM IEDS,#0000_0101B
:
:
:
IEDS
[0E6_H]
Figure 19-6 External Interrupt Block Diagram
Ext. Interrupt Edge Selection
Register
IEDS
ADDRESS : 0E6_H
RESET VALUE : ----0000
W WW W
Response Time
The INT0 and INT1 edge are latched into INT0IF and
INT3IF at every machine cycle. The values are not actually
polled by the circuitry until the next machine cycle. If a re-
quest is active and conditions are right for it to be acknowl-
edged, a hardware subroutine call to the requested service
routine will be the next instruction to be executed. The
DIV itself takes twelve cycles. Thus, a minimum of twelve
complete machine cycles elapse between activation of an
external interrupt request and the beginning of execution
of the first instruction of the service routine.
shows interrupt response timings.
INT1 edge select
00: Int. disable
01: falling
10: rising
11: both
INT0 edge select
00: Int. disable
01: falling
10: rising
11: both
max. 12 f_OSC
8 f_OSC
Interrupt Interrupt
goes latched
active
Interrupt
processing
Interrupt
routine
Figure 19-7 Interrupt Response Timing Diagram
Nov. 1999 Ver 0.0
preliminary
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