GMS81C2020 Datasheet, PDF (60/92 Pages) Hynix Semiconductor – CMOS Single-Chip 8-Bit Microcontroller with A/D Converter & VFD Driver

GMS81C2020/GMS81C2120
Hyundai Micro Electro nics
16. Serial Peripheral Interface
The Serial Peripheral Interface (SPI) module is a serial in-
terface useful for communicating with other peripheral of
microcontroller devices. These peripheral devices may be
SPI Mode Control Register
SIOM
POL
IOSW
SM1
SM0
SCK1
serial EEPROMs, shift registers, display drivers, A/D con-
verters, etc.
SCK0 SIOST SIOSF
ADDRESS : E0H
RESET VALUE : 00000000
POL
IOSW
SM[1:0]
Serial Clock Polarity Selection bit.
0 : Data Transmission at falling edge
( Received data latch at rising edge )
1 : Data Transmission at rising edge
( Received data latch at falling edge )
SCK[1:0]
Serial Input Pin Selection bit
0 : SIN(R54) Pin Selection
1 : SOUT(R55) Pin Selection
SIOST
Serial Operation Mode Selection bits
00 : Normal Port ( R55, R54, R53 )
01 : Transmit Mode ( SOUT,R54, SCLK )
10 : Receive Mode ( R55, SIN, SCLK )
11 : Transmit & Receive Mode ( SOUT, SIN, SCLK )
SIOSF
Serial Clock Selection bits
00 : fXI ÷ 4
01 : fXI ÷ 16
10 : TMR0OV ( Overflow of Timer 0 )
11 : External Clock
Serial Transmit Start bit
0 : Disable
1 : Start ( After one SCLK, becomes “0” )
Serial Transmit Status bit
0 : During Transmission
1 : Finished
SPI Data Register
SIOR
ADDRESS : E1H
RESET VALUE : Undefined
T0CK[2:0] ^POL
[SIOM.7]
fXI
÷4
÷16
TMR0OV
(Timer 0 overflow)
MUX
1
0
R53/SCLK
SCLKI
SCLKO
SCLK
[R5FUNC.3]
SIOST
0 : Disable
1 : Clear and Start
SPI Control Circuit
SIOSF
0 : Process
1 : Completed
Octal Counter ( 3-Bit )
SPIIF
SPI
INTERRUPT
R54/SIN
IOSW
MSB
LSB
SIOR ( 8-Bit )
IOSW
R55/SOUT
Figure 16-1 SPI Registers and Block Diagram
The SPI allows 8-bits of data to be synchronously transmit-
ted and received. To accomplish communication, typically
three pins are used:
- Serial Data In
- Serial Data Out
- Serial Clock
R54/SIN
R55/SOUT
R53/SCLK
The serial data transfer operation mode is decided by set-
ting the SM1 and SM0 of SPI Mode Control Register, and
the transfer clock rate is decided by setting the SCK1 and
SCK0 of SPI Mode Control Register as shown in Figure
16-1 . And the polarity of transfer clock is selected by set-
60
preliminary
Nov. 1999 Ver 0.0