GMS81C2020 Datasheet, PDF(33/92 Page) Hynix Semiconductor – CMOS Single-Chip 8-Bit Microcontroller with A/D Converter & VFD Driver

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GMS81C2020 Datasheet, PDF (33/92 Pages) Hynix Semiconductor – CMOS Single-Chip 8-Bit Microcontroller with A/D Converter & VFD Driver

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Hyundai Micro Electronics

GMS81C2020/GMS81C2120

Address Name

C0H R0

C1H R0IO

C2H R1

C3H R1IO

C4H R2

C5H R2IO

C6H R3

C7H R3IO

C8H R4

C9H R4IO

CAH R5

CBH R5IO

CCH R6

CDH R6IO

CEH R7

CFH R7IO

D0H TM0

D1H

T0/TDR0/

CDR0

D2H TM1

D3H

TDR1/

T1PPR

D4H

T1/CDR1/

T1PDR

D5H PWM1HR

DEH BUR

E0H SIOM

E1H SIOR

E2H IENH

E3H IENL

E4H IRQH

E5H IRQL

E6H IEDS

EAH ADCM

EBH ADCR

ECH BITR1

ECH CKCTLR1

Bit 7

Bit 6

Bit 5

Bit 4

R0 Port Data Register (Bit[7:0])

R0 Port Direction Register (Bit[7:0])

R1 Port Data Register (Bit[7:0])

R1 Port Direction Register (Bit[7:0])

R2 Port Data Register (Bit[7:0])

R2 Port Direction Register (Bit[7:0])

R3 Port Data Register (Bit[5:0])

R3 Port Direction Register (Bit[5:0])

R4 Port Data Register (Bit[3:0])

R4 Port Direction Register (Bit[3:0])

R5 Port Data Register (Bit[7:0])

R5 Port Direction Register (Bit[7:0])

R6 Port Data Register (Bit[7:0])

R6 Port Direction Register (Bit[7:0])

R7 Port Data Register (Bit[5:0])

R7 Port Direction Register (Bit[5:0])

CAP0 T0CK2

Bit 3

T0CK1

Bit 2

T0CK0

Timer0 Register / Timer0 Data Register / Capture0 Data Register

POL

16BIT PWM1E CAP1 T1CK1 T1CK0

Timer1 Data Register / PWM1 Period Register

Timer1 Register / Capture1 Data Register / PWM1 Duty Register

PWM1 High Register(Bit[3:0])

BUCK1 BUCK0 BUR5

POL

IOSW

SM1

SPI DATA REGISTER

INT0E INT1E

T0E

ADE

WDTE

BITE

INT0IF INT1IF

T0IF

ADIF

WDTIF

BITIF

BUR4

SM0

T1E

SPIE

T1IF

SPIIF

ADEN

ADS3

ADS2

ADC Result Data Register

Basic Interval Timer Data Register

WAKEUP RCWDT WDTON

BUR3

SCK1

IED1H

ADS1

BTCL

BUR2

SCK0

IED1L

ADS0

BTS2

Bit 1

T0CN

T1CN

BUR1

SIOST

IED0H

ADST

BTS1

Bit 0

T0ST

T1ST

BUR0

SIOSF

IED0L

ADSF

BTS0

Table 11-3 Control Registers of GMS81C2020

These registers of shaded area can not be accessed by bit manipulation instruction as " SET1, CLR1 ", but should be accessed by

Nov. 1999 Ver 0.0

preliminary

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