HY5DU121622BT-5 Datasheet, PDF (7/30 Pages) Hynix Semiconductor – 512Mb(32Mx16) gDDR SDRAM

HY5DU121622BT(P)
SIMPLIFIED COMMAND TRUTH TABLE
Command
CKEn-1 CKEn
CS
RAS CAS
WE
ADDR
A10/
AP
BA
Note
Extended Mode Register Set
H
X
L
L
L
L
OP code
1,2
Mode Register Set
H
Device Deselect
H
No Operation
Bank Active
H
Read
H
Read with Autoprecharge
Write
H
Write with Autoprecharge
X
L
L
L
L
OP code
1,2
H
X
X
X
X
X
1
L
H
H
H
X
L
L
H
H
RA
V
1
L
1
X
L
H
L
H
CA
V
H
1,3
L
1
X
L
H
L
L
CA
V
H
1,4
Precharge All Banks
H
Precharge selected Bank
H
X
1,5
X
L
L
H
L
X
L
V
1
Read Burst Stop
H
X
L
H
H
L
X
1
Auto Refresh
H
H
L
L
L
H
X
1
Entry
H
L
L
L
L
H
1
Self Refresh
Exit
L
H
X
X
X
H
X
1
L
H
H
H
H
X
X
X
1
Entry
H
L
Precharge Power
Down Mode
L
H
H
H
1
X
H
X
X
X
1
Exit
L
H
L
H
H
H
1
H
X
X
X
1
Active Power
Entry
H
Down Mode
L
L
V
V
V
X
1
Exit
L
H
X
1
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
Note :
1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Register setting duing Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time
(tWR) is needed to guarantee that the last data has been completely written.
5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
precharged.
Rev. 0.2 / Mar. 2005
7