HY5DU121622BT-5 Datasheet, PDF (23/30 Pages) Hynix Semiconductor – 512Mb(32Mx16) gDDR SDRAM

HY5DU121622BT(P)
DC CHARACTERISTICS II (TA=0 to 70 ^oC, Voltage referenced to VSS = 0V)
32Mx16
Parameter Symbol
Test Condition
Operating Current
Operating Current
Precharge Power
Down Standby
Current
Idle Standby Current
Active Power Down
Standby Current
Active Standby
Current
Operating Current
Operating Current
Auto Refresh Current
Self Refresh Current
Operating Current -
Four Bank Operation
Random Read
Current
IDD0
IDD1
IDD2P
IDD2N
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
IDD7A
One bank; Active - Precharge ; tRC=tRC(min);
tCK=tCK(min) ; DQ,DM and DQS inputs changing twice per
clock cycle; address and control inputs changing once per
clock cycle
One bank; Active - Read - Precharge;
Burst Length=2; tRC=tRC(min); tCK=tCK(min); address
and control inputs changing once per clock cycle
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
Vin>=Vih(min) or Vin=<Vil(max) for DQ, DQS and DM
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock
cycle
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle;
tCK=tCK(min); IOUT=0mA
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle;
tCK=tCK(min); DQ, DM and DQS inputs changing twice per
clock cycle
tRC=tRFC(min) - 14*tCK for DDR400 at 200Mhz
CKE =< 0.2V; External clock on; tCK=tCK(min)
Four bank interleaving with BL=4, Refer to the following
page for detailed test condition
4banks active read with activate every 20ns, AP(Auto
Precharge) read every 20ns, BL=4, tRCD=3, IOUT=0 mA,
100% DQ, DM and DQS inputs changing twice per clock
cycle; 100% addresses changing once per clock cycle
Speed
5
6
150
140
200
180
10
10
35
35
12
12
50
45
280
250
330
280
300
280
5
5
540
460
540
460
Unit Note
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Rev. 0.2 / Mar. 2005
23