HY5DU121622BT-5 Datasheet, PDF (27/30 Pages) Hynix Semiconductor – 512Mb(32Mx16) gDDR SDRAM

Parameter
Write DQS High Level Width
Write DQS Low Level Width
Clock to First Rising edge of DQS-In
Data-In Setup Time to DQS-In (DQ & DM)
Data-in Hold Time to DQS-In (DQ & DM)
Read DQS Preamble Time
Read DQS Postamble Time
Write DQS Preamble Setup Time
Write DQS Preamble Hold Time
Write DQS Postamble Time
Mode Register Set Delay
Exit Self Refresh to Any Execute Command
Average Periodic Refresh Interval
HY5DU121622BT(P)
Symbol
tDQSH
tDQSL
tDQSS
tDS
tDH
tRPRE
tRPST
tWPRES
tWPREH
tWPST
tMRD
tXSC
tREFI
5
Min
Max
0.4
0.6
0.4
0.6
0.72
1.28
0.4
-
0.4
-
0.9
1.1
0.4
0.6
0
-
0.25
-
0.4
0.6
2
-
200
-
-
7.8
6
Min
Max
0.4
0.6
0.4
0.6
0.72
1.28
0.45
-
0.45
-
0.9
1.1
0.4
0.6
0
-
0.25
-
0.4
0.6
2
-
200
-
-
7.8
-Continue-
Unit Note
CK
CK
CK
ns 6,7,11
,
ns 12,13
CK
CK
CK
CK
CK
CK
CK
8
us
Note :
1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
Input Setup / Hold Slew-rate
Delta tIS
Delta tIH
V/ns
ps
ps
0.5
0
0
0.4
+50
0
0.3
+100
0
5. CK, /CK slew rates are >=1.0V/ns
6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by
design or tester correlation.
7. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.
8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
Rev. 0.2 / Mar. 2005
27