HY5DU121622BT-5 Datasheet, PDF (26/30 Pages) Hynix Semiconductor – 512Mb(32Mx16) gDDR SDRAM

HY5DU121622BT(P)
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter
Row Cycle Time
Auto Refresh Row Cycle Time
Row Active Time
Active to Read with Auto Precharge Delay
Row Address to Column Address Delay
Row Active to Row Active Delay
Column Address to Column Address Delay
Row Precharge Time
Write Recovery Time
Internal Write to Read Command Delay
Auto Precharge Write Recovery + Precharge Time
System Clock Cycle Time
CL = 3
Clock High Level Width
Clock Low Level Width
Data-Out edge to Clock edge Skew
DQS-Out edge to Clock edge Skew
DQS-Out edge to Data-Out edge Skew
Data-Out hold time from DQS
Clock Half Period
Data Hold Skew Factor
Input Setup Time (fast slew rate)
Input Hold Time (fast slew rate)
Input Setup Time (slow slew rate)
Input Hold Time (slow slew rate)
Symbol
5
Min
Max
tRC
12
-
tRFC
14
-
tRAS
40
100K
tRAP
tRCD or
tRASmin
-
tRCD
4
-
tRRD
2
-
tCCD
1
-
tRP
4
-
tWR
3
-
tWTR
2
-
tDAL
7
-
tCK
5
10
tCH
0.45
0.55
tCL
0.45
0.55
tAC
-0.7
0.7
tDQSCK
-0.7
0.7
tDQSQ
-
0.4
tQH
tHP
-tQHS
-
tHP
min
(tCL,tCH)
-
tQHS
-
0.4
tIS
0.6
-
tIH
0.6
-
tIS
0.7
-
tIH
0.7
-
6
Min
Max
10
-
12
-
42
100K
tRCD or
tRASmin
-
3
-
2
-
1
-
3
-
3
-
2
-
6
-
6
10
0.45
0.55
0.45
0.55
-0.7
0.7
-0.7
0.7
-
0.45
tHP
-tQHS
-
min
(tCL,tCH)
-
-
0.45
0.75
-
0.75
-
0.8
-
0.8
-
Unit Note
CK
CK
ns
ns
16
CK
CK
CK
CK
ns
CK
CK
15
ns
CK
CK
ns
ns
ns
ns
1,10
ns
1,9
ns
10
ns
2,3,5,6
ns
ns
2,4,5,6
ns
Rev. 0.2 / Mar. 2005
26