HY5S7B2ALFP-6 Datasheet, PDF (5/53 Pages) Hynix Semiconductor – 512M (16Mx32bit) Mobile SDRAM

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512Mbit (16Mx32bit) Mobile SDR Memory
HY5S7B2ALF(P) Series
FEATURES
● Standard SDRAM Protocol
● Clock Synchronization Operation
- All the commands registered on positive edge of basic input clock (CLK)
● MULTIBANK OPERATION - Internal 4bank operation
- During burst Read or Write operation, burst Read or Write for a different bank is performed.
- During burst Read or Write operation, a different bank is activated and burst Read or Write
for that bank is performed
- During auto precharge burst Read or Write, burst Read or Write for a different bank is performed
● Power Supply Voltage : VDD = 1.8V, VDDQ = 1.8V
● LVCMOS compatible I/O Interface
● Low Voltage interface to reduce I/O power
● Programmable burst length: 1, 2, 4, 8 or full page
● Programmable Burst Type : sequential or interleaved
● Programmable CAS latency of 3 or 2
● Programmable Drive Strength
● Low Power Features
- Programmable PASR(Partial Array Self Refresh)
- Auto TCSR (Temperature Compensated Self Refresh)
- Programmable DS (Drive Strength)
- Deep Power Down Mode
● -25^oC ~ 85^oC Operation Temperature
- Extended Temp. : -25^oC ~ 85^oC
● Package Type : 90ball, 0.8mm pitch FBGA (Lead Free, Lead), 8 x 13 [mm²], t=1.0mm max
HY5S7B2ALFP : Lead Free
512M SDRAM ORDERING INFORMATION
Part Number
HY5S7B2ALFP-6
HY5S7B2ALFP-H
HY5S7B2ALFP-S
Clock Frequency
CAS
Latency
Organization
Interface
90Ball
FBGA
166MHz
3
133MHz
3
4banks x 4Mb x 32 LVCMOS Lead Free
105MHz
3
Rev 1.2 / Nov. 2008
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