HY5S7B2ALFP-6 Datasheet, PDF (12/53 Pages) Hynix Semiconductor – 512M (16Mx32bit) Mobile SDRAM

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512Mbit (16Mx32bit) Mobile SDR Memory
HY5S7B2ALF(P) Series
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter
System Clock
Cycle Time
CAS Latency=3
CAS Latency=2
Clock High Pulse Width
Clock Low Pulse Width
CAS Latency=3
Access Time From Clock
CAS Latency=2
Data-out Hold Time
Data-Input Setup Time
Data-Input Hold Time
Address Setup Time
Address Hold Time
CKE Setup Time
CKE Hold Time
Command Setup Time
Command Hold Time
CLK to Data Output in Low-Z Time
CLK to Data Output in
High-Z Time
CAS Latency=3
CAS Latency=2
166MHz
133MHz
105MHz
Symbol
Unit Note
Min Max Min Max Min Max
tCK3
6.0 1000 7.5 1000 9.5 1000 ns
tCK2
12 1000 12 1000 15 1000 ns
tCHW
2.0
-
2.5
-
3.0
-
ns
1
tCLW
2.0
-
2.5
-
3.0
-
ns
1
tAC3
- 5.4 - 6.0 - 7.0 ns 2, 3
tAC2
- 6.0
- 8.0
-
10 ns 2, 3
tOH
2.6
- 2.6
-
2.6
-
ns
3
tDS
2.0
-
2.0
-
3.0
-
ns
1
tDH
1.0
-
1.0
-
1.5
-
ns
1
tAS
2.0
-
2.0
-
3.0
-
ns
1
tAH
1.0
-
1.0
-
1.5
-
ns
1
tCKS
2.0
-
2.0
-
3.0
-
ns
1
tCKH
1.0
-
1.0
-
1.5
-
ns
1
tCS
2.0
-
2.0
-
3.0
-
ns
1
tCH
1.0
-
1.0
-
1.5
-
ns
1
tOLZ
1.0
-
1.0
-
1.0
-
ns
tOHZ3
5.4
6.0
7.0 ns
tOHZ2
6.0
8.0
10 ns
Notes :
1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.
2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns
should be added to the parameter.
3. Output Load : 30pF+No termination
● AC high level input voltage / low level input voltage : 1.6 / 0.2V
● Input timing measurement reference level : 0.9V
Output
Z = 50Ω
● Transition time (input rise and fall time) : 0.5ns
● Output timing measurement reference level : 0.9V
Output Load
● Output load : CL = 30pF
1.6V
CLK
0.9V
30pF
0.2V
1.6V
Input 0.9V
0.2V
Output
tCK
tCH
tCL
tSETUP tHOLD
tAC
tOH
Rev 1.2 / Nov. 2008
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