HMT84GL7AMR4A Datasheet, PDF (5/36 Pages) Hynix Semiconductor – DDR3(L) SDRAM Load Reduced DIMM Based on 4Gb A-die

Pin Descriptions
Pin Name
Description
CK0
Clock Input, positive line
Num
ber
1
CK0
Clock Input, negative line
1
CK1
Clock Input, positive line
1
CK1
Clock Input, negative line
1
CKE[1:0] Clock Enables
2
Clock Enables
CKE[3:2], ^{On Die Termination}
ODT[1], TEST ^{Memory bus tool (Not Con-}
2
nected and Not Useable on
DIMMs)
RAS
Row Address Strobe
1
CAS
Column Address Strobe
1
WE
Write Enable
1
S[1:0]
Chip Selects
2
S[3:2], A17, Chip Selects
A16
Address Inputs
2
A[9:0],A11,
A[15:13]
Address Inputs
14
A10/AP Address Input/Autoprecharge 1
A12/BC Address Input/Burst chop
1
BA[2:0]
SDRAM Bank Addresses
3
SCL
Serial Presence Detect (SPD)
Clock Input
1
SDA
SPD Data Input/Output
1
SA[2:0] SPD Address Inputs
3
Pin Name
Description
Par_In
Err_Out
ODT[0]
DQ[63:0]
CB[7:0]
Parity bit for the Address and Con-
trol bus
Parity error found on the Address
and Control bus
On Die Termination Inputs
Data Input/Output
Data check bits Input/Output
DQS[8:0] Data strobes
DQS[8:0]
DM[8:0]/
DQS[17:9],
TDQS[17:9]
DQS[17:9],
TDQS[17:9]
EVENT
TEST
Data strobes, negative line
Data Masks / Data strobes,
Termination data strobes
Data Masks / Data strobes,
Termination data strobes
Reserved for optional hardware
temperature sensing
Memory bus test tool (Not Con-
nected and Not Usable on DIMMs)
RESET
Register and SDRAM control pin
V_DD
V_SS
V_REFDQ
V_REFCA
V_TT
V_DDSPD
Power Supply
Ground
Reference Voltage for DQ
Reference Voltage for CA
Termination Voltage
SPD Power
Num
ber
1
1
1
64
8
9
9
9
9
1
1
1
22
59
1
1
4
1
Rev. 0.3 / Jul. 2013
5