HMT84GL7AMR4A Datasheet, PDF (17/36 Pages) Hynix Semiconductor – DDR3(L) SDRAM Load Reduced DIMM Based on 4Gb A-die

DDR3-1066 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 21.
Speed Bin
DDR3-1066F
CL - nRCD - nRP
Parameter
Symbol
Internal read command to
first data
t_AA
min
13.125
7-7-7
max
20
ACT to internal read or
write delay time
t_RCD
13.125
—
PRE command period
t_RP
13.125
—
ACT to ACT or REF
command period
t_RC
ACT to PRE command
period
t_RAS
CL = 6
CWL = 5
CWL = 6
t_CK(AVG)
t_CK(AVG)
CL = 7
CWL = 5
CWL = 6
t_CK(AVG)
t_CK(AVG)
CL = 8
CWL = 5
CWL = 6
t_CK(AVG)
t_CK(AVG)
Supported CL Settings
Supported CWL Settings
50.625
—
37.5
2.5
1.875
1.875
9 * tREFI
Reserved
Reserved
Reserved
6, 7, 8
5, 6
3.3
< 2.5
< 2.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
n_CK
n_CK
Note
1,2,3,6
1,2,3,4
4
1,2,3,4
4
1,2,3
Rev. 0.3 / Jul. 2013
17