HMT84GL7AMR4A Datasheet, PDF (16/36 Pages) Hynix Semiconductor – DDR3(L) SDRAM Load Reduced DIMM Based on 4Gb A-die

Standard Speed Bins
DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDR3-800 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 21.
Speed Bin
CL - nRCD - nRP
Parameter
Internal read command to first data
Symbol
t_AA
DDR3-800E
6-6-6
min
max
15
20
ACT to internal read or write delay time
t_RCD
15
—
PRE command period
t_RP
15
—
ACT to ACT or REF command period
t_RC
52.5
—
ACT to PRE command period
CL = 6
CWL = 5
Supported CL Settings
Supported CWL Settings
t_RAS
t_CK(AVG)
37.5
2.5
9 * tREFI
3.3
6
5
Unit
Notes
ns
ns
ns
ns
ns
ns
1,2,3
n_CK
n_CK
Rev. 0.3 / Jul. 2013
16