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HMT84GL7AMR4A Datasheet, PDF (20/36 Pages) Hynix Semiconductor – DDR3(L) SDRAM Load Reduced DIMM Based on 4Gb A-die
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DDR3-1866 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 21.
Speed Bin
DDR3-1866M
CL - nRCD - nRP
Parameter
Symbol
Internal read command
to first data
tAA
ACT to internal read or
write delay time
tRCD
PRE command period
tRP
ACT to PRE command
period
tRAS
ACT to ACT or PRE
command period
tRC
CWL = 5
CL = 6 CWL = 6
CWL = 7,8,9
CWL = 5
CL = 7 CWL = 6
CWL = 7,8,9
CWL = 5
CL = 8
CWL = 6
CWL = 7
CWL = 8,9
CWL = 5, 6
CL = 9
CWL = 7
CWL = 8
CWL = 9
CWL = 5, 6
CL = 10 CWL = 7
CWL = 8
CWL = 5,6,7
CL = 11 CWL = 8
CWL = 9
CL = 12
CWL = 5,6,7,8
CWL = 9
CL = 13
CWL = 5,6,7,8
CWL = 9
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
Supported CL Settings
Supported CWL Settings
min
13.91
(13.125)5,11
13.91
(13.125)5,11
13.91
(13.125)5,11
13-13-13
max
20
—
—
34
9 * tREFI
47.91
(47.125)5,11
-
2.5
3.3
Reserved
Reserved
Reserved
1.875
< 2.5
Reserved
Reserved
1.875
< 2.5
Reserved
Reserved
Reserved
1.5
<1.875
Reserved
Reserved
Reserved
1.5
<1.875
Reserved
Reserved
1.25
<1.5
Reserved
Reserved
Reserved
Reserved
1.07
<1.25
6, 7, 8, 9, 10, 11, 13
5, 6, 7, 8, 9
Rev. 0.3 / Jul. 2013
Unit
Note
ns
ns
ns
ns
ns
ns
1,2,3,9
ns
1,2,3,4,9
ns
4
ns
4
ns
1,2,3,4,9
ns
4
ns
4
ns
1,2,3,9
ns
1,2,3,4,9
ns
4
ns
4
ns
1,2,3,4,9
ns
1,2,3,4,9
ns
4
ns
4
ns
1,2,3,9
ns
1,2,3,4,9
ns
4
ns
1,2,3,4,9
ns
1,2,3,4
ns
4
ns
1,2,3,4
ns
4
ns
1, 2, 3
nCK
nCK
20
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