HMT84GL7AMR4A Datasheet, PDF (12/36 Pages) Hynix Semiconductor – DDR3(L) SDRAM Load Reduced DIMM Based on 4Gb A-die

32GB, 4Gx72 Module(4Rank of x4) - page3
CS[3:0]
BA[2:0]
A[15:0]
RAS
CAS
WE
CKE[3:0]
ODT[1:0]
CK0
CK0
CK1
CK1
PAR_IN
RESET
CS2A → CS0: SDRAMs D[8:0] CS3A → CS0: SDRAMs D[35:27]
CS0A → CS1: SDRAMs D[8:0] CS1A → CS1: SDRAMs D[35:27]
M
e
m
o
CS2B → CS0: SDRAMs D[17:9] CS3B → CS0: SDRAMs D[26:18]
CS0B → CS1: SDRAMs D[17:9] CS1B → CS1: SDRAMs D[26:18]
BA[2:0]A → BA[2:0]: SDRAMs D[8:0], D[35:27]
BA[2:0]B → BA[2:0]: SDRAMs D[26:9]
r
y
A[15:0]A → A[15:0]: SDRAMs D[8:0], D[35:27]
A[15:0]B → A[15:0]: SDRAMs D[26:9]
RASA → RAS: SDRAMs D[8:0], D[35:27]
RASB → RAS: SDRAMs D[26:9]
B
CASA → CAS: SDRAMs D[8:0], D[35:27]
u
CASB → CAS: SDRAMs D[26:9]
f
WEA → WE: SDRAMs D[8:0], D[35:27]
f
WEB → We: SDRAMs D[26:9]
e
CKE2A → CKE0: D[8:0] CKE0A → CKE1: D[8:0]
r
CKE3A → CKE0: D[26:18] CKE1A → CKE1: D[26:18]
CKE2B → CKE0: D[17:9] CKE0B → CKE1: D[17:9]
CKE3B → CKE0: D[35:27] CKE1B → CKE1: D[35:27]
ODT0A → ODT1: SDRAMs D[8:0]
ODT1A → ODT1: SDRAMs D[35:27]
ODT0B → ODT1: SDRAMs D[17:9]
ODT1B → ODT1: SDRAMs D[26:18]
CK0 → CK: SDRAMs D[8:0]
CK1 → CK: SDRAMs D[35:27]
CK2 → CK: SDRAMs D[17:9]
CK3 → CK: SDRAMs D[26:18]
CK0 → CK: SDRAMs D[8:0]
CK1 → CK: SDRAMs D[35:27]
CK2 → CK: SDRAMs D[17:9]
CK3 → CK: SDRAMs D[26:18]
Err_Out
QRESET: All SDRAMs
1. CK0 and CK0 are terminated with 120 Ohms ±5% resistor.
2. CK1 and CK1 are terminated with 120 Ohms ±5% resistor, but is not used.
3. Unless othersiwe noted resistors are 22 Ohms ±5%
Rev. 0.3 / Jul. 2013
12