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HMT451U6MFR8C Datasheet, PDF (5/55 Pages) Hynix Semiconductor – DDR3 SDRAM Unbuffered DIMMs Based on 4Gb M-Die | |||
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Pin Descriptions
Pin Name
Description
Pin Name
Description
A0âA15
BA0âBA2
RAS
CAS
WE
S0âS1
CKE0âCKE1
ODT0âODT1
DQ0âDQ63
CB0âCB7
DQS0âDQS8
DQS0âDQS8
DM0âDM8
CK0âCK1
CK0âCK1
SDRAM address bus
SDRAM bank select
SDRAM row address strobe
SDRAM column address strobe
SDRAM write enable
DIMM Rank Select Lines
SDRAM clock enable lines
On-die termination control lines
DIMM memory data bus
DIMM ECC check bits
SDRAM data strobes
(positive line of differential pair)
SDRAM data strobes
(negative line of differential pair)
SDRAM data masks/high data strobes
(x8-based x72 DIMMs)
SDRAM clocks
(positive line of differential pair)
SDRAM clocks
(negative line of differential pair)
SCL
SDA
SA0âSA2
VDD*
VDDQ*
VREFDQ
VREFCA
VSS
VDDSPD
NC
TEST
RESET
VTT
RSVD
-
I2C serial bus clock for EEPROM
I2C serial bus data line for EEPROM
I2C slave address select for EEPROM
SDRAM core power supply
SDRAM I/O Driver power supply
SDRAM I/O reference supply
SDRAM command/address reference
supply
Power supply return (ground)
Serial EEPROM positive power supply
Spare pins (no connect)
Memory bus analysis tools
(unused on memory DIMMS)
Set DRAMs to Known State
SDRAM I/O termination supply
Reserved for future use
-
*The VDD and VDDQ pins are tied common to a single power-plane on these designs
Rev. 1.1 / Jul. 2013
5
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